SED1520D0A Datasheet, PDF (20/52 Pages) List of Unclassifed Manufacturers – DOT MATRIX LCD DRIVER

3.2 – 3.2.2
3.0 Pin Configuration
3.2 PIN DESCRIPTION
Product name
SED1520FOA
SED1521FOA
SED1520FAA
SED1521FAA
74
OSC1
CS
CS
CS
75
OSC2
CL
CL
CL
Pin No.
96~100, 1~11
COM0~COM15*
SEG76~SEG61
COM0~COM15*
SEG76~SEG61
93
M/S
SEG79
M/S
SEG79
94
V4
SEG78
V4
SEG78
* Master LSI common outputs COM0–COM15 correspond to slave LSI outputs COM31–COM16.
95
V1
SEG77
V1
SEG77
3.2.1 Power Signals
VDD
Connected to +5V power. Common to MPU power pin VCC.
VSS
0V, connected to system GND.
V1–V5
Multi-level power used to drive LCDs. Voltage specified to each LCD cell is divided by
resistors or impedance-converted by an operational amplifier before being applied. Each
voltage to be applied must be based on VDD, while fulfilling the following conditions:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
3.2.2 System Bus Interface Signals
D7–D0
8–bit, tri-state, bi-directional I/O bus. Normally, connected to the data bus of an 8–/16–
bit standard microcomputer.
A0
Input pin. Normally, the LSB of the MPU address bus is connected to this input pin to
provide data/command selection.
0: Display control data on D7–D0
1: Display data on D7–D0
RES
Input pin. The SED1520 can be reset or initialized by setting RES to low level (if it is
interfaced with a 68 family MPU) or high level (if with an 80 family MPU). This reset op-
eration occurs when an edge of the RES signal is sensed. The level input selects the
type of interface with the 68 or 80 family MPU:
High level: Interface with 68 family MPU
Low level: Interface with 80 family MPU
20 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: [phone] • Fax: [phone]