SDA9401 Datasheet, PDF (9/69 Pages) List of Unclassifed Manufacturers – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9401
6 System description
6.1 Input sync controller (ISC)
Input signals
Signals
HIN
Pin number
23
VIN
22
SYNCEN
29
Description
horizontal synchronization signal (polarity
programmable, I²C bus parameter 01h
HINPOL, default: high active)
vertical synchronization signal (polarity
programmable, I²C bus parameter 01h
VINPOL, default: high active)
enable signal for HIN and VIN signal, low
active (see also chapter Input format con-
version (IFC) on page 12)
The input sync controller derives framing signals from the H- and V-Sync for the input data
processing. The framing signals depend on different parameters and mark the active picture area.
Input parameter
HIN
VIN
lines
per
field
pixels per line
NALIP+PD
(VERPOS*2)
(ALPFIP*2)
(VERWIDTH*2)
(HORPOS* (HORWIDTH*32)*
32)*CLK1
CLK1
(NAPIPDL*4 +
NAPIPPH + PD)*
CLK1
(APPLIP*32)*CLK1
PD - Processing Delay
The distance between the incoming H-syncs in system clocks of clk1 must be even.
Micronas
9
Preliminary Data Sheet