SDA9401 Datasheet, PDF (49/69 Pages) List of Unclassifed Manufacturers – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9401
6.8.4 Detailed description
Default values are underlined.
Bit
D7...D6
D5
D4
D3
D2...D1
D0
Subaddress 00
Name
FORMAT
FIEINV
VCRMODE
PIMODE
NAPIPPH
(LSBs of
NAPLIP)
Function
Input format:
11: full CCIR 656
10: CCIR 656 only data, H- and V-sync according CCIR656
01: CCIR 656 only data, H- and V-sync according PAL/NTSC
00: 4:2:2
Field polarity inversion:
1: Field A=1, Field B=0
0: Field A=0, Field B=1
Input filtering of the incoming field signal:
1: on
0: off
Picture insert mode (see VERWIDTH, VERPOS, HORWIDTH, HORPOS):
1: on
0: off
Number of not active pixels from external HIN to the input data in system
clocks of CLK1:
Number(HIN to input data) = (NAPIPDL*4+NAPIPPH+8) [NAPIPPH = 0]
TWOIN
Chrominance input format:
1: 2’s complement input (-128...127)
0: unsigned input (0...255)
inside the SDA 9401 the data are always processed as unsigned data
Bit
D7...D2
D1
D0
Name
VINDEL
VINPOL
HINPOL
Subaddress 01
Function
VIN input delay:
Delay(VIN to internal V-sync) = (128 * VINDEL + 1)*Tclk1 [VINDEL = 0]
VIN polarity:
1: low active
0: high active
HIN polarity:
1: low active
0: high active
Micronas
49
Preliminary Data Sheet