SDA9401 Datasheet, PDF (41/69 Pages) List of Unclassifed Manufacturers – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9401
Data 4:2:2 Parallel
Pin
UVIN7 U₀₇
V₀₇
UVIN6 U₀₆
V₀₆
UVIN5 U₀₅
V₀₅
UVIN4 U₀₄
V₀₄
UVIN3 U₀₃
V₀₃
UVIN2 U₀₂
V₀₂
UVIN1 U₀₁
V₀₁
UVIN0 U₀₀
V₀₀
X ab: X: signal component a: sample number b: bit number
6.7 High data rate processing (HDR)
The output signal can be vertically expanded. The expansion as well as the different scan rate
conversion algorithms are processed in the HDR block. For the vertical expansion line memories
are used. If the operation frequency X1/CLK2 is higher than 27 MHz plus 10%, the line memories
will not work correctly any more. In this case only simple processing will be possible. Simple
processing means, that the vertical expansion must be disabled.
The table below defines the internal expansion factor ZOOM depending on the RMODE and
VERINT parameter.
Output write parameter: VERINT
VERINT
I²C-bus
parameter
I²C-bus
parameter
RMODE
0
1
ZOOM
2*(VERINT+1)
(VERINT+1)
The reachable expansion factors are listed in the table below in case of VDECON=0 and
VDECON=2 (vertical compression of the input signal with factor 1.0 and 1.5).
Micronas
41
Preliminary Data Sheet