SDA9401 Datasheet, PDF (51/69 Pages) List of Unclassifed Manufacturers – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9401
Bit
D7...D0
Name
OPDEL
Subaddress 06
Function
Output processing delay (in number of lines):
Delay(VIN to VOUT) = (OPDEL + 1) * Tline [OPDEL = 170]
Bit
D7...D0
Name
VERWIDTH
Subaddress 07
Function
Vertical width of inserted picture in input lines:
Vertical width = (2 * VERWIDTH) [VERWIDTH = 0]
Bit
D7...D0
Name
VERPOS
Subaddress 08
Function
Vertical position of inserted picture in input lines:
Vertical position = (2 * VERPOS) + NALIP + 3 [VERPOS = 0]
Bit
D7...D2
D1...D0
Name
HORWIDTH
PLL1RA(1...0)
Subaddress 09
Function
Horizontal width of inserted picture in system clocks of CLK1:
Horizontal width = (32 * HORWIDTH) [HORWIDTH = 0]
PLL1 range, only for test purposes [PPL1RA=0]
Bit
D7...D2
D1...D0
Name
HORPOS
PLL1RA(3...2)
Subaddress 0A
Function
Horizontal position of inserted picture in system clocks of CLK1:
Horizontal position = (32 * HORPOS) + (4 * NAPIPDL + NAPIPPH + 8)
[HORPOS = 0]
PLL1 range, only for test purposes [PPL1RA=0]
Micronas
51
Preliminary Data Sheet