SDA9401 Datasheet, PDF (32/69 Pages) List of Unclassifed Manufacturers – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9401
Timing diagram of output signals
X1/CLK2
HOUT
64 * Tx1/clk2
YOUT
PPLOP * 2 Tx1/clk2
e.g. 432 * 2 / 27 MHz = 32 µs
x
y0 y1 y2 y3 y4 y5
UVOUT
x
u0 v0 u2 v2 u4 v4
((HOUTDEL + 1) * 4 + PD)* Tx1/clk2
HREF
YOUT
UVOUT
APPLOP * 16 * Tx1/clk2
e.g. 45 * 16 = 720 Tx1/clk2
x
YB YB YB YB y0 y1
x
UB VB UB VB u0 v4
((HOUTDEL + 1 + NAPOP) * 4 + PD)* Tx1/clk2
ALOP
ym-2 ym-1
um-2 vm-´2
YB YB
UB VB
x
x
m=APPL*16
x
x
m=APPL*16
Output write parameter
Parameter
HOUTFR
1: freerun
0: locked
mode
YBORDER
UBORDER
VBORDER
CAPP
00: k = 0
01: k = 8
10: k = 16
11: k = 24
Subaddress
Description
14h
HOUT generator mode select
17h
Y border value (four MSB of the 8 bit colour)
18h
U border value (four MSB of the 8 bit colour)
18h
V border value (four MSB of the 8 bit colour)
10h
Reducing factor for the Active Pixels Per Line Value
(APPL)
Number of active pixels per line = 16 * APPL - 2*k
6.5.2 VOUT generator
The VOUT generator has two operation modes, which can be selected by the parameter VOUTFR.
The VOUT signal is active high (VOUTPOL=0) for two output lines. In the freerunning-mode the
VOUT signal is generated depending on the LPFOP parameter.
In the locked-mode the VOUT signal is synchronized by the incoming V-Sync signal VIN (means the
internal VIN delayed by the parameter OPDEL, see also Input sync controller (ISC) on page 9). The
RMODE parameter (raster mode 1: progressive, 0: interlaced) determines the scan rate conversion
Micronas
32
Preliminary Data Sheet