SDA9401 Datasheet, PDF (31/69 Pages) List of Unclassifed Manufacturers – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9401
The next paragraphs describe the HOUT and VOUT generator in more detail. Both generators have
a so called “locked-mode” and “freerunning-mode”. Not all combinations of the modi make sense.
The table below shows ingenious configurations.
Ingenious configurations of the HOUT and VOUT generator
Mode
“H-and-V-locked”
“H-freerunning-V-locked”
“H-and-V-freerunning”
HOUTFR
0
1
1
VOUTFR
0
0
1
CLK11EN
1
1
1
CLK21EN
1
0
0
6.5.1 HOUT generator
The HOUT generator has two operation modes, which can be selected by the parameter HOUTFR.
The HOUT signal is active high (HOUTPOL=0) for 64 clock cycles (X1/CLK2). In the freerunning-
mode the HOUT signal is generated depending on the PPLOP parameter. In the locked-mode the
HOUT signal is locked on the incoming H-Sync signal HIN. The polarity of the HOUT signal is
programmable by the parameter HOUTPOL.
The HREF signal marks the active part of a line. The figure below shows the timing relation of the
HOUT and the HREF signal. The distance is programmable by the parameter HOUTDEL. PD
means processing delay of the internal data processing (PD=36 X1/CLK2 clocks). The length of the
active part is determined by the parameter APPLOP. If the number of the active pixels (internal
parameter APPL, see also Horizontal compression on page 17) is smaller than the number of the
displayed pixels (e.g. displaying a 4:3 source on a 16:9 screen), a coloured border can be defined
using the NAPOP parameter. The border colour is defined by the parameters YBORDER,
UBORDER and VBORDER. To avoid transition artifacts of digital filters the number of active pixels
per line (parameter APPL) can be symmetrically reduced using the CAPP parameter. The figure
below shows also the internal signal ALOP, which marks the active pixels of the line.
Micronas
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Preliminary Data Sheet