NT68P61A Datasheet, PDF (8/48 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (24K OTP ROM Type)

NT68P61A
3. OTP ROM: 24K X 8 bits
The OTP ROM storing application program code, executed by 6502 CPU, has a capacity of 24K X 8 bits, addressed from
$A000 to $FFFF. It is programmed by the universal EPROM writer through a conversion adapter.
In PROGRAMMING mode, OTP ROM is integrated with system and cannot be directly accessed. When using the OTP
ROM alone, first enter the PROGRAMMING mode by setting: RESET = VPP.
At this time, through multiplex pins, normal procedures are used to program and verify the OTP ROM block with the
universal programmer.
OTP ROM Mega Cell D.C. Electrical Characteristics (READ Mode)
(VDD = 5V , TA = 25°C, unless otherwise specified)
Symbol
VIH
VIL
IIL
IOH
IOL
IDD
ISTB1
Parameter
Input Voltage
Min.
VDD-0.3
-0.3
Typ.
Max.
VDD+0.3
0.3
Unit
V
V
Input Current
+/-10
µA
-400
µA
Output Voltage
1
µA
Operating Current
Standby Current
1
µA
100
µA
Test Conditions
Note
1
1
VDD =5V, VOH = 4.5V
VDD =5V, VOL = 0.5V
f = 4MHz
2
3
Notes: 1. All inputs and outputs are CMOS compatible
2. f = 4MHz, Iout = 0mA, CE = VIH, VDD = 5V
3. CE = VIH, OE = VIL, VDD = 5V
OTP ROM Mega Cell l A.C. Electrical Characteristics (READ Mode)
(VDD = 5V, TA = 25°C, unless otherwise specified)
Symbol
Tcyc
T12
Tacc
Tce
Tst
Toh
Parameter
Cycle Time
Nonoverlap Time to PH1 & PH2
Address Access Time
OTPCE to Output Valid
Output Data Setup Time
Output Data Hold Time
Min.
250
5
20
0
Max.
65
145
145
Unit
Conditions
ns
ns
ns
4.5V < VDD < 5.5V
ns
ns
ns
OTP ROM MEGA CELL A.C. Test Conditions
Output Load
Input Pulse Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level
1 CMOS Gate and CL = 10pF
10ns Max.
0V to 5V
Inputs 0V and 5V outputs 0.3V and 4.7V
8