NT68P61A Datasheet, PDF (39/48 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (24K OTP ROM Type)

NT68P61A
STOP condition: When SCL & SDA lines have been
released (remain in 'HIGH' state), DDC2B data transfer
is always terminated by a STOP condition generated by
external device. A STOP signal is defined as a low to
high transition of SDA while SCL is in HIGH state. When
there is a STOP condition, NT68P61A will set the 'STOP'
bit to '1' and user can poll this status bit to control
DDC2B transmission at any time. This bit keeps '1' until
user clears it. Notice the SCL and SDA lines must
conform to I²C bus specifications. (Refer to Figure 26).
Refer to the standard I²C bus specification for details.
Changing to DDC1 mode: After an external device
terminates DDC2 transmission, set MDI/ 2 to 1 for
changing to DCC1 mode. When the SCL line has been
released (pulled-up), user can force NT68P61A to DDC1
mode communication at any time. This function is
supporting the 'error' recovery protocol in the VESA DDC
standard Ver 2.0.
Control bit description:
Addr. Register INIT Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0005 MD CON 07H
-
-
-
-
-
-
S/ C
MD1/ 2
R
-
-
-
-
INSEN
HSEL
S/ C
MD1/ 2 W
$000F
IEX
00H
-
-
IEINTS IEINTD IEINTA IEINTR IEINTE IEINTV W
$0010 IRQX 00H
-
-
IRQINTS IRQINTD IRQINTA IRQINTR IRQINTE IRQINTV R
$0011 CLR FLG 00H CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV W
$0013 II ADR FFH AR7
AR6
AR5
AR4
AR3
AR2
AR1
-
W
$0014 II DAT 00H SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0 RW
$0015 II STS 08H
-
-
START
STOP
RXAK
START
STOP
ENDDC
TRX
-
R
W
MDCON control register:
MD1/ 2 : Select the DDC mode - '1' for DDC1 and '0' for
DDC2B mode. System will be DDC1 mode by
default.
When transmission mode is changed form
DDC1 to DDC2B, system will automatically
clear
this bit.
IEX control register:
In DDC2 mode, user use INTS, INTA & INTD interrupt
and II_STS control register to control DDC2B
transmission.
II_DAT control register: Data buffer for transmission
II_ADR control register: User can define the address of
DDC2B device. If an external
device sends the same address
data as this control register
(calling NT68P61A), NT68P61A
will generate an INTA interrupt.
II_STS control register:
ENDDC : When clearing this bit, the system will activate
DDC transmission. P30 and P31 will switch to
SDA and SCL pin.
TRX: In the READ mode of DDC2B transmission, user
must set this bit '1'.
RXAK: In the WRITE mode of DDC2B transmission,
after
one byte has been sent out to the SDA line,
there will be an INTD interrupt. At INTD interrupt
service routine, user can check this bit to see if
external device has responded to NT68P61A.
39