NT68P61A Datasheet, PDF (19/48 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (24K OTP ROM Type)

NT68P61A
Addr. Register INIT Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$000C ENDAC FFH _{ENAD1 ENAD0 ENDK13 ENDK12 ENDK11 ENDK10 ENDK9 ENDK8} W
$0018 DACH0 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0019 DACH1 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$001A DACH2 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$001B DACH3 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$001C DACH4 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$001D DACH5 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$001E DACH6 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$001F DACH7 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0020 DACH8 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0021 DACH9 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0022 DACH10 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0023 DACH11 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0024 DACH12 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
$0025 DACH13 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
DAC control register ($000C) and DAC value register ($0018 - $0025)
Control Bit Description:
Addr. Register INIT Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$000C ENDAC FFH _{ENAD1 ENAD0 ENDK13 ENDK12 ENDK11 ENDK10 ENDK9 ENDK8} W
$0018 DACH0 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW
ENDK8 : Enable DAC channel 8; When clearing this bit
to '0', the I/O port, P00, will change to DAC channel 8.
When setting this bit to '1', the I/O port will
restore to P00.
ENDK9 - ENDK13 : The manipulation is the same as
ENDK8 bit, and control DAC channel 9 - 13.
DACH0 (DKVL0 - DKVL7): Setting DAC output waveform
of DAC channel 8. Please check Figure 3 for the timing
diagram
and wave table.
DACH1 - DACH13: The manipulation is the same as
DACH0 register, and control DAC channel 1 - 13.
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