NT68P61A Datasheet, PDF (33/48 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (24K OTP ROM Type)

NT68P61A
13.3. Power Saving Mode Detect:
The VIDEO mode is listed below. Power saving is from mode 2 to mode 4. All modes can be detected by setting the
control register properly. Refer to Figure 15 control flow chart for software reference.
Mode
(1) Normal
(2) Stand by
(3) Suspend
(4) Off
H-Sync
Active
Inactive
Active
Inactive
V-Sync
Active
Active
Inactive
Inactive
Control bit description:
Addr. Register INIT Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0005 MD CON 07H
-
-
-
-
-
-
S/ C
MD1/ 2 ^R
-
-
-
-
INSEN
HSEL
S/ C
MD1/ 2 ^W
$0006 HV CON 2FH HCNTOV VCNTOV HSYNCI VSYNCI HPOLI
VPOLI
HPOLO
R
VPOLO W
$0007 HCNT L 00H HCL7
HCL6
HCL5
HCL4
HCL3
HCL2
HCL1
HCL0 R
$0008 HCNT H 00H
-
-
-
-
HCH3
HCH2
HCH1
HCH0 R
$0009 VCNT L 00H VCL7
VCL6
VCL5
VCL4
VCL3
VCL2
VCL1
VCL0 R
$000A VCNT H 00H
-
-
-
-
VCH3
VCH2
VCH1
VCH0 R
$000B SYNCON FFH _{NOHALF ENHALF}
-
FRUN FRFREQ ^HALFPOL ENH
ENV
W
$0011 CLR FLG 00H CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV W
MDCON control register:
S/ C : The SYNC MODE control. If the input of V & H
Sync are separate signals, set this bit to
'1' (system default). If the input is composite
signal, clear this bit. Under the COMPOSITE
mode,
NT68P61A will extract the V Sync form H Sync
signal.
HSEL : When clearing this bit, system will reset
HCNTL|H counter to zero. The number of Hsync
pulse at the 8.192ms interval is obtained.
INSEN : User can clear this bit for inserting Hsync pulse
when processing the composite signal. System
will disable this function after reset.
HVCON control register:
HCNTOV: The overflow bit of H Sync. After setting
HSEL bit '1' without any input Vsync pulses and
there are more than 4096 Hsync pulses
coming ,this bit will be set. It will keep '1' and
user can clears it by setting CLRHOV bit to '1'
at the CLRFLG control register. After cleared,
the H Sync counter will reset to '0' and start
counting for every Hsync pulse.
VCNTOV: The overflow bit of V Sync. The operation is
the same as HCNTOV. After cleared, the
Vsync counter will reset to '0' and start
counting for every 8µs.
HSYNCI & VSYNCI:User can instantaneously detect
input of H & V Sync pulse at any
time.
HPOLI & VPOLI: The polarity of input H & V Sync pulse
- '1' for positive polarity and '0' for
negative polarity.
HPOLO & VPOLO:To control the output polarity of H & V
Sync pulse - '1' for positive polarity
and '0' for negative polarity.
HCNTL|H & VCNTL|H control registers:
The 12 bits counter for H & V Sync pulse.
SYNCON control register:
ENH & ENV : Enable the output of H & V Sync. The P06
& P07 will switch to VSYNCO & HSYNCO
output.
FRUN : Open free run signal at the VSYNCO & HSYNCO
output.
FRFREQ : Select the free run frequency of H Sync
output.
ENHALF : P12 & P13 will switch to HALFHO & HALFHI
pin. The HALFHO will output the half signal at
the HALFHI pin with 50% duty.
NOHALF : User must clear ENHALF first. The HALFHO
will output the same signal at the HALFHI
pin.
HALFPOL: User must clear ENHALF first and control
the
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