NT68P61A Datasheet, PDF (35/48 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (24K OTP ROM Type)

NT68P61A
15. I²C Bus Interface: DDC1 & DDC2B Slave Mode
I²C bus interface is a two-wire, bi-directional serial bus which provides a simple, efficient way for data communication
between devices. Its structure minimizes the cost of connecting various peripheral devices. In short, the wired-AND
connection of all I²C interface to I²C bus is the most important structure. Two modes of operation have been implemented
in NT68P61A: UNI-DIRECTIONAL mode (DDC1 mode) and BI-DIRECTIONAL mode (DDC2B mode). If the MD1/ 2 bit is
set to '1', the device will operate in the DDC1 mode, and if the MD 1/ 2 bit is cleared to '0', the device will operate in the
DDC2B mode. All of these I²C functions will be activated only when ENDDC bit clears to '0' (in IISTS register). When I²C
bus
function is activated, the P30 & P31 will switch to SCL & SDA pin. System works on the DDC1 mode transmission default.
The SCL pin will remain high and SDA will transfer one bit of data at every rising edge of Vsync pulse.
0
SCL
SDA
Shift Register (IIDAT)
clock source
1
VSYNC
MD1/2
15.1. DDC1 Bus Interface
Vsync input and SDA pin: In DDC1 data transfer, the
Vsync input pin is used as an input clock for data
transmission and SDA output pin, as serial data line.
This function comprises of two data buffers: one is a
preloaded data buffer for user placing one bit of data in
advance, and one is shift register for system shifting out
one bit of data to the SDA pin. These two data buffer
cooperate properly. Refer to Figure 18. After system
reset, the I²C bus interface is in DDC1 mode.
Data transfer: In advance, put one byte transmitted data
into IIDAT register and activate I²C bus by setting
ENDDC bit to '0' and open INTD interrupt source by
setting IEINTD to '1'. On the first 9 rising edge of Vsync,
system will shift out any invalid bit in shift register to
SDA pin to empty shift register. When shift register is
empty and on next rising edge of Vsync, it will load data
in the IIDAT register to internal shift register. At the same
time, NT68P61A will shift out MSB bit and generate an
INTD interrupt to remind user to replace next byte data
into IIDAT register. After eight rising clocks, there are
eight bits shifted out in proper order and the shift register
becomes empty again. At the ninth rising clock, it will
shift the ninth bit (null bit '1') out to SDA. And on the next
rising edge of Vsync clock, system will generate a INTD
interrupt again. NT68P61A will also load new data in the
IIDAT register to internal shift register and shift out one
bit immediately. User must input new data to IIDAT
register properly before the shift register is empty (the
next INTD interrupt).
Vsync clock: In the separate sync signal, the Vsync pulse
is used as a data transfer clock. Its frequency allows
25KHz maximum. If no Vsync input signal is found,
NT68P61A can not transmit any data to SDA pin
regardless what the Vsync has extracted from composite
Hsync signal.
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