NT68P61A Datasheet, PDF (36/48 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (24K OTP ROM Type)

NT68P61A
Control bit description:
Addr. Register INIT Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0005 MD CON 07H
-
-
-
-
-
-
S/ C
MD1/ 2 R
-
-
-
-
INSEN
HSEL
S/ C
MD1/ 2 W
$000F
IEX
00H
-
-
IEINTS IEINTD IEINTA IEINTR IEINTE IEINTV W
$0010 IRQX 00H
-
-
IRQINTS IRQINTD IRQINTA IRQINTR IRQINTE IRQINTV R
$0011 CLR FLG 00H CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV W
$0014 II DAT 00H SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0 RW
$0015 II STS 08H
-
-
START
STOP
RXAK
-
R
START
STOP
ENDDC
TRX
TXAK W
MDCON control register:
MD1/ 2 : Select the DDC mode - '1' for DDC1 and '0' for DDC2B mode. System will be DDC1 mode by default.
When transmission mode is changed form DDC1 to DDC2B, system automatically clears this bit.
IEX control register:
At DDC1 mode, only open INTD interrupt, as well as open INTS interrupt to detect if has changed to DDC2B mode.
II_DAT control register: Data buffer for transmission.
II_STS control register:
ENDDC : When clearing this bit, system will activate DDC transmission. P30 & P31 will switch to SDA & SCL pin.
ENDDC
(in IISTS register)
Vsync Pulse
INTV
Load data in the IIDAT register to shift register
123 4
ååå
ååå
912 34 5678 91 2
ååå
ååå
ååå
INTD
ååå
User can load next byte data to IIDAT register
SDA
Invalid data ^{å å å} 8 7 6
5
å å å 1 Null 8 7 6
5 4 3 2 1 ^Null 8
7^{å å å}
Bit
Bit
Shift
register
87
MSB
65 43
First Byte Data
21
LSB
Second Byte Data
Figure 22. DDC1 Mode Timing Diagram
36