NT68P61A Datasheet, PDF (37/48 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (24K OTP ROM Type)

15.2 DDC2B Slave Mode Bus Interface
The DDC2B I²C Bus Interface features are as follows:
- SLAVE mode (NT68P61A addressed by a master
which drive SCL signal)
- Fully compatible with I²C bus standard
- Interrupt and generation of acknowledge handled by
user for communication
- Interrupt driven byte by byte data transfer
- Calling address identification interrupt
- Detection of START and STOP signals
Enable I²C and INTS: The NT68P61A included the use in
applications requiring storage and serial transmission of
configuration and control information. User can place
address data into IIADR register and set IEINTS to '1' (in
IEX register) in advance. In the DDC1 mode (after
clearing ENDDC to '0') and when the low level on the
SCL pin occurs, NT68P61A will remind user by
NT68P61A
generating a INTS interrupt and switch to DDC2B mode
automatically. When user sets MD1/ 2 to '1' at this time,
the NT68P61A will still proceed with a DDC1
communication. The DDC2B bus consists of two wires,
SCL and SDA; SCL is for the data transmission clock
and SDA is for the data line. Data transfers follow the
format shown in Figure 19. The standard communication
of I²C bus protocol includes four parts: a START signal,
slave ADDRESS, transferred data (proceed byte by byte)
and a STOP signal. In the wired-AND connection, any
slow devices can hold the SCL line LOW to force the fast
device into a wait state until the slow device is ready for
the next bit or byte transfer in a type of handshake
procedure.
START
CONDITION
SDA
STOP
CONDITION
SCL
ååå
1-7
ååå
8
9
1-7
ååå
8
9
1-7
8
9
ADDRESS R/W ACK
DATA
ACK
DATA
ACK
IIDAT Reg.
bit stream
876
5
4 1 ^{å å å} _{A C K}
8
7
6
5 4 3 2 1 ACK 8
7^{å å å}
MSB
LSB
MSB
LSB
MSB
Figure 23. DDC2B Data Transfer
37