NT68P61A Datasheet, PDF (21/48 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor (24K OTP ROM Type)

NT68P61A
11. Interrupt Controller
The µC will complete the current instruction being
executed before recognizing the interrupt request. At this
time, the interrupt mask bit in the status register will be
examined. If the interrupt mask bit is not set, µC will
begin interrupt sequence. The program counter and
processor status register are stored in the stack. µC will
then set the interrupt mask flag HIGH so that no further
interrupts occur. At the end of this cycle, the program
counter will be loaded from addresses $FFFE & $FFFF,
transferring program control to the memory vector
located at these addresses.
Six interrupt sources are available in this system:
- INTV INT (Vsync INT): Rising edge of every Vsync
pulse
- INTE INT (External INT): Rising edge of external
interrupt pulse
- INTMR INT (Timer INT): As the Base Timer counter
overflow and counting from $FF to $00
- INTA INT (Address Matched INT): External device
calling NT68P61A in DDC2 mode communication
- INTD INT (Shift Register INT): Shift register is
empty or receiving a new byte data in DDC1 & DDC2
mode communication
- INTS INT (SCL Go-Low INT): External device
proceed a DDC2 communication
Three memory mapped registers are used to control the
interrupt operation. The IRQX is set by the rising edge of
Control bit description:
external pins (INTV & INTE), base timer overflow (INTR),
SCL line go-low (INTS), and serial bus interrupt (INTA &
INTD). The serial bus interrupt is generated by the I²C
circuit as described in under I²C bus interface sections.
The interrupt enable (IEX) bit will effects the interrupt
process if the IRQX has already been set. Once IEX bit
is set, its corresponding interrupt will generate an
interrupt source for 6502 CPU. The IRQX will be set no
matter the IEX bit enable or not. The interrupt request is
generated when IRQX and IEX are both '1'. The IRQX
remains in HIGH state unless the CLRIRQ register is
cleared (write '1' to correspondent bit in CLRIRQ
register). The interrupt enable register (IEX) and interrupt
request register (IRQX) are memory mapped registers
which can only be accessed or tested by program. These
registers are cleared to '0' at initialization after the chip is
reset .
When interrupt occurs, CPU jumps to $FFFE & $FFFF to
execute interrupt service routine and finds which one of
the interrupt sources is active by checking the IRQX.
Upon entering the interrupt service routine, the IRQX that
caused the interrupt service must be cleared in the
interrupt service routine program. CPU clears IRQX by
writing '1' to the corresponding bit in CLRIRQ register. If
more than one interrupt is pending and waiting to be
served, each is executed by priority. Priority is defined by
the programmer.
ADDR. REGISTER INIT Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$000F
IEX
00H
-
-
IEINTS IEINTD IEINTA IEINTR IEINTE IEINTV W
$0010
IRQX
00H
-
-
IRQINTS IRQINTD IRQINTA IRQINTR IRQINTE IRQINTV R
$0011 CLR FLG 00H CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV W
IRQINTS is the interrupt flag for SCL- At DDC2B TRANSMISSION mode, it is set when SCL line changes from '1' to '0'.
IEINTS enable 6502 interrupt for INTS. - When this bit is set to '1' and IRQINTS flag is set, 6502 will accept interrupt
source and jump to interrupt service routine assigned by interrupt vector.
CLRINTS clears INTS interrupt flag. - Before returning from interrupt service routine, this flag must be cleared.
The manipulation of other interrupt source is the same as INTS.
CLRHOV & CLRVOV: Clear the overflow flag of H/V counter and reset H/V counter to zero.
21