ACD82124 Datasheet, PDF (7/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

False Carrier Events
If the RXER signal in the MII interface is asserted when
the receive data valid (RXDV) signal is not asserted,
the port is considered to have a false carrier event. If
a port has more than two consecutive false carrier
events, the port will automatically be partitioned from
the switch system. The partitioned port will be re-acti-
vated if it has been idling for 33,000 BT or it has re-
ceived a valid frame.
Frame Forwarding
If the first bit of the destination address is 0, the frame
is handled as a unicast frame. The destination ad-
dress is passed to the Address Resolution Logic, which
returns a destination port number to identify which port
the frame should be forwarded to. If Address Resolu-
tion Logic cannot find any match for the destination
address, the frame will be treated as a frame with un-
known DA. The frame will be processed in one of two
ways. If the option flood-to-all-port is enabled, the
switch will forward the frame to all ports within the same
VLAN of the source port, except the source port itself.
If the option is not enabled, the frame will be forwarded
to the ‘dumping port’ of the source port VLAN only.
The dumping port is determined by the VLAN ID of the
source port. If the source port belongs to multiple
VLANs, a frame with unknown DA will then be for-
warded to multiple dumping ports of the VLANs.
If the first bit of the destination address is a 1, the
frame is handled as a multicast or broadcast frame.
The ACD82124 does not differentiate a multicast packet
from a broadcast packet except the reserved bridge
management group address, as specified in table 3.5
of the IEEE 802.1d standard. The destination ports of
the broadcast frame is all ports within the same VLAN
except the source port itself.
The order of all broadcast frames with respect to the
unicast frames is strictly enforced by the ACD82124.
Frame Transmission
The ACD82124 transmits all frames in accordance to
IEEE 802.3 standard. The ACD82124 will send the
frames with a guaranteed minimum interframe gap of
96 BT, even if the received frames have an IFG less
than the minimum requirement. Before the transmit
process is started, the MAC logic will check if the chan-
nel has been silent for more than 64 BT. Within the 64
BT silent window, the transmission process will defer
on any receiving process. If the channel has been
silent for more than 64 BT, the MAC will wait an addi-
tional 32 BT before starting the transmit process. In
the event that the carrier sense signal is asserted by
the MII during the wait period, the MAC logic will gen-
erate a JAM signal to cause a forced collision.
The MAC logic will abort the transmit process if a colli-
sion is detected through the assertion of the Col signal
of the MII. Re-transmission of the frame is scheduled
in accordance to IEEE 802.3’s truncated binary expo-
nential backoff algorithm. If the transmit process has
encountered 16 consecutive collisions, an excessive
collision error is reported, and the ACD82124 will try
to re-transmit the frame, unless the drop-on-exces-
sive-collision option of the port is enabled. It will first
reset the number of collisions to zero and then start
the transmission after 96 BT of interframe gap. If drop-
on-excessive-collision is enabled, the ACD82124 will
not try to re-transmit the frame after 16 consecutive
collisions. If a collision is detected after 512 BT of the
transmission, a late collision error will be reported, but
the frame will still be retransmitted after proper backoff
time.
Frame Generation
During a transmit process, frame data is read out from
the memory buffer and is forwarded to the destination
port’s PHY device in nibbles. 7 bytes of preamble sig-
nal (10101010) will be generated first followed by the
SFD (10101011), and then the frame data and 4 bytes
of FCS are sent out last.
Frame Buffer
All ports of the ACD82124 work in Store-And-Forward
mode so that all ports can support both 10Mbps and
100Mbps data speed. The ACD82124 utilizes a global
memory buffer pool, which is shared by all ports. The
device has a unique architecture that inherits the ad-
vantage of both output buffer-based and input buffer-
based switches. An output buffer-based switch stores
the received data only once into the memory, and hence
has a short latency. Whereas an input buffer-based
switch typically has more efficient flow control.
Flow Control
Under half duplex mode of operation, when the switch
cannot handle the receiving of an incoming frame, a
collision is generated by sending a jam pattern to the
sending party to force it to back off and re-transmit the
frame later. Back pressure flow control is applied to a
port when its reserved-buffer is full and no more shared
buffer is available, or when starvation control is active.
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