ACD82124 Datasheet, PDF (3/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

1. GENERAL DESCRIPTION
The ACD82124 is a single chip implementation of a 24
port 10/100 Ethernet switch system intended for IEEE
802.3 and 802.3u compatible networks. The device
includes 24 independent 10/100 MACs. Each MAC
interfaces with an external PMD/PHY device through a
standard MII interface. Speed can be automatically
configured through the MDIO port. Each port can op-
erate at either 10Mbps or 100Mbps. The core logic of
the ACD82124, implemented with patent pending
BASIQ (Bandwidth Assured Switching with Intelligent
Queuing) technology, can simultaneously process 24
asynchronous 10/100Mbps port traffic. The Queue
Manager inside the ACD82124 provides the capability
of routing traffic with the same order of sequence,
without any packet loss.
A complete 24 port 10/100 switch can be built with the
use of the ACD82124, 10/100 PHY and ASRAM. The
MAC addresses can be expanded from the built-in 2K
to 11K by the use of ACD’s external ARL chip
(ACD80800 Address Resolution Logic). Advanced net-
work management features can be supported with the
use of ACD’s MIB (ACD80900 Management Informa-
tion Base) chip.
2. FEATURES
• 24 ports 10/100 auto-sensing with MII interface
• Half-duplex operation, with optional full-duplex con-
figuration by combining 2 adjacent ports
• 2.4 Gbps aggregated throughput
• True non-blocking switch architecture
• Flexible port configuration (up to 12 full duplex 10/
100 ports, up to 24 half duplex 10/100 ports)
• Built-in storage of 2,000 MAC address
• Automatic source address learning
• Zero-Packet Loss back-pressure flow control
• Store-and-forward switch mode
• Port based V-LAN support
• UART type CPU management interface
• Supports up to 11K MAC addresses with the
ACD80800
• RMON and SNMP support with ACD80900
• Status LEDs: Link, Speed, Full Duplex, Transmit,
Receive, Collision and Frame Error
• Reversible MII option for CPU and expansion port
interface
• Wire speed forwarding rate
• 576 pin BGA package
• 3.3V power supply, 3.3V I/O with 5V tolerance
3. SYSTEM BLOCK DIAGRAM
PMD/
PHY-0
PMD/
PHY-1
FIFO
FIFO
FIFO
FIFO
MAC-0
MAC-1
Buffer
Buffer
Buffer
Buffer
PMD/
PHY-22
PMD/
PHY-23
FIFO
FIFO
FIFO
FIFO
MAC-22
MAC-23
Buffer
Buffer
Buffer
Buffer
Lookup Engine
(2K MAC Addr.)
BIST Handler
LED Controller
MX
Queue Manager
DMX
ARL Interface
ACD82124
ARL
ACD80800
(11K MAC Addr.)
(optional)
SRAM Interface
SRAM
MIB Interface
MIB
ACD80900
(optional)
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