ACD82124 Datasheet, PDF (43/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

4. INTERFACE DESCRIPTION
CPU Interface
The CPU can communicate with the ARL through the
UART interface of the switch IC. The management CPU
can send command to the ARL by writing into associ-
ated registers, and retrieve result from ARL by read-
ing corresponding registers. The registers are de-
scribed in the section of “Register Description.” The
CPU interface signals are described by table-1:
Table-1: CPU Interface
Name
I/O
Description
UARTDI
I
UART input data line.
UARTDO O
UART output data line.
UARTDI is used by the control CPU to send command
into the ARL. The baud rate will be automatically de-
tected by the ARL. The result will be returned through
the UARTDO line with the detected baud rate. The for-
mat of the command packet is shown as follows:
Header
Address
Data
Checksum
UARTDO is used to return the result of command ex-
ecution to the CPU. The format of the result packet is
shown as follows:
Header
Address
Data
Checksum
where:
•
•
•
•
Header is further defined as:
b1:b0 - read or write, 01 for read, 11
for write
b4:b2 - device number, 000 to 111 (0
to 7)
b7:b5 - device type, 010 for ARL
Address - 8-bit value for address of the
selected register
Data - 32-bit value, only the LSB is used
for read operation, all 0 for write opera-
tion
Checksum - 8-bit value of XOR of all bytes
The ARL will always check the CMD header to see if
both the device type and the device number matches
with its setting. If not, it ignores the command and will
not generate any response to this command.
where:
•
•
•
•
Header is further defined as:
b1:b0 - read or write, 01 for read, 11
for write
b4:b2 - device number, 000 to 111 (0
to 7, same as the host switch con-
troller)
b7:b5 - device type, 010 for ARL
Address - 8-bit value used to select the
register to access
Data - 32-bit value, only the LSB is used
for write operation, all 0 for read opera-
tion
Checksum - 8-bit value of XOR of all bytes
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