ACD82124 Datasheet, PDF (11/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

6. INTERFACE DESCRIPTION
MII Interface (MII)
The ACD82124 communicates with the external 10/
100 Ethernet transceivers through standard MII inter-
face. The signals of MII interface are described in
table-6.1:
Table-6.1: MII Interface Signals
Name
Type
Description
PxCRS
I
Carrier sense
PxRXDV
I
Receive data valid
PxRXCLK
I
Receive clock (25/2.5 MHz)
PxRXERR I
Receive error
PxRXD0
I
Receive data bit 0
PxRXD1
I
Receive data bit 1
PxRXD2
I
Receive data bit 2
PxRXD3
I
Receive data bit 3
PxCOL
I
Collision indication
PxTXEN
O
Transmit data valid
PxTXCLK
I
Transmit clock (25/2.5 MHz)
PxTXD0
O
Transmit data bit 0
PxTXD1
O
Transmit data bit 1
PxTXD2
O
Transmit data bit 2
PxTXD3
O
Transmit data bit 3
Table-6.2: Reversed MII Interface Signals
Name Type
Description
PxCRSR
O Carrier sense
PxRXDVR
I
Transmit data valid
PxRXCLKR O Transmit clock (25/2.5 MHz)
PxRXERR I
Not-Ready (Input)
PxRXD0R
I
Transmit data bit 0
PxRXD1R
I
Transmit data bit 1
PxRXD2R
I
Transmit data bit 2
PxRXD3R
I
Transmit data bit 3
PxCOLR
O
Collision Indication/
Not-Ready (Output)
PxTXENR O Receive data valid
PxTXCLKR O Receive clock (25/2.5 MHz)
PxTXD0R O Receive data bit 0
PxTXD1R O Receive data bit 1
PxTXD2R O Receive data bit 2
PxTXD3R O Receive data bit 3
For reversed MII interface, signal PxRXDVR, and
PxRXD0R through PxRXD3R are clocked out by the
falling edge of PxRXCLKR. Signal PxTXENR, and
PxTXD0R through PxTXD3R can be sampled by the
falling edge or rising edge of PxTXCLKR, depends on
the setting of bit 9 of Register 16. The timing behavior
is described in the chapter of “Timing Description.“
For MII interface, signal PxRXDV, PxRXER and
PxRXD0 through PxRXD3 are sampled by the rising
edge of PxRXCLK. Signal PxTXEN, and PxTXD0
through PxTXD3 are clocked out by the falling edge of
PxTXCLK. The detailed timing requirement is described
in the chapter of “Timing Description”
Ports 0,1, 2, 3, 4, 5, 6, 7, 22 and 23 can be config-
ured as reversed MII ports (Register 28, the Reversed
MII Enable register). These ports, when configured as
“normal” MII, have the same characteristics as all other
MII ports. However, when configured as reversed MII
interface, they will behave logically like a PHY device,
and can interface directly with a MAC device. The
signal of reversed MII interface are described by table-
6.2:
Note: * Collision Indication for half-duplex mode.
Not-Ready (output) for full duplex mode.
PHY Management Interface
All control and status registers of the PHY devices are
accessible through the PHY management interface.
The interface consists of two signals: MDC and MDIO,
which are described in Table-6.3.
Table-6.3: PHY Management Interface Signals
Name Type
Description
MDC O PHY management clock (1.25MHz)
MDIO I/O PHY management data
Frames transmitted on MDIO has the following format
(Table-6.4):
Table-6.4: MDIO Format
Operation
PRE
ST
Write
1…1
01
Read
1…1
01
OP
PHY-ID REG-AD
TA
01
aaaaa
rrrrr
10
10
aaaaa
rrrrr
Z0
DATA
d…d
d…d
IDLE
Z
Z
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