ACD82124 Datasheet, PDF (17/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

PAR register (register 3)
The PAR register indicates the presence of the parti-
tioned ports and the port ID. A port can be automati-
cally partitioned if there is a consecutive false carrier
event, an excessive collision or a jabber. This register
is automatically cleared after each read. Table-7.3 lists
all the bits of this register.
Table-7.3: PAR Register
Bit
Description
0
0 - Port 0 not partitioned.
1 - Port 0 partitioned.
1
0 - Port 1 not partitioned.
1 - Port 1 partitioned.
2
0 - Port 2 not partitioned.
1 - Port 2 partitioned.
3
0 - Port 3 not partitioned.
1 - Port 3 partitioned.
4
0 - Port 4 not partitioned.
1 - Port 4 partitioned.
5
0 - Port 5 not partitioned.
1 - Port 5 partitioned.
6
0 - Port 6 not partitioned.
1 - Port 6 partitioned.
7
0 - Port 7 not partitioned.
1 - Port 7 partitioned.
8
0 - Port 8 not partitioned.
1 - Port 8 partitioned.
9
0 - Port 9 not partitioned.
1 - Port 9 partitioned.
10
0 - Port 10 not partitioned.
1 - Port 10 partitioned.
11
0 - Port 11 not partitioned.
1 - Port 11 partitioned.
12
0 - Port 12 not partitioned.
1 - Port 12 partitioned.
13
0 - Port 13 not partitioned.
1 - Port 13 partitioned.
14
0 - Port 14 not partitioned.
1 - Port 14 partitioned.
15
0 - Port 15 not partitioned.
1 - Port 15 partitioned.
16
0 - Port 16 not partitioned.
1 - Port 16 partitioned.
17
0 - Port 17 not partitioned.
1 - Port 17 partitioned.
18
0 - Port 18 not partitioned.
1 - Port 18 partitioned.
19
0 - Port 19 not partitioned.
1 - Port 19 partitioned.
20
0 - Port 20 not partitioned.
1 - Port 20 partitioned.
21
0 - Port 21 not partitioned.
1 - Port 21 partitioned.
22
0 - Port 22 not partitioned.
1 - Port 22 partitioned.
23
0 - Port 23 not partitioned.
1 - Port 23 partitioned.
Default
0
PMERR register (register 4)
The PMERR register indicates the presence of PHYs
that have failed to respond to the PHY Management
command issued through the MDIO line. This register
is automatically cleared after each read. Table-7.4
describes all the bit of this register.
Table-7.4: PMERR Register
Bit
Description
0
0 - Port 0 PHY responded
1 - Port 0 PHY failed to respond
1
0 - Port 1 PHY responded
1 - Port 1 PHY failed to respond
2
0 - Port 2 PHY responded
1 - Port 2 PHY failed to respond
3
0 - Port 3 PHY responded
1 - Port 3 PHY failed to respond
4
0 - Port 4 PHY responded
1 - Port 4 PHY failed to respond
5
0 - Port 5 PHY responded
1 - Port 5 PHY failed to respond
6
0 - Port 6 PHY responded
1 - Port 6 PHY failed to respond
7
0 - Port 7 PHY responded
1 - Port 7 PHY failed to respond
8
0 - Port 8 PHY responded
1 - Port 8 PHY failed to respond
9
0 - Port 9 PHY responded
1 - Port 9 PHY failed to respond
10
0 - Port 10 PHY responded
1 - Port 10 PHY failed to respond
11
0 - Port 11 PHY responded
1 - Port 11 PHY failed to respond
12 ^{0 - Port 12 PHY responded}
1 - Port 12 PHY failed to respond
13
0 - Port 13 PHY responded
1 - Port 13 PHY failed to respond
14
0 - Port 14 PHY responded
1 - Port 14 PHY failed to respond
15 ^{0 - Port 15 PHY responded}
1 - Port 15 PHY failed to respond
16
0 - Port 16 PHY responded
1 - Port 16 PHY failed to respond
17
0 - Port 17 PHY responded
1 - Port 17 PHY failed to respond
18 ^{0 - Port 18 PHY responded}
1 - Port 18 PHY failed to respond
19
0 - Port 19 PHY responded
1 - Port 19 PHY failed to respond
20
0 - Port 20 PHY responded
1 - Port 20 PHY failed to respond
21 ^{0 - Port 21 PHY responded}
1 - Port 21 PHY failed to respond
22
0 - Port 22 PHY responded
1 - Port 22 PHY failed to respond
23
0 - Port 23 PHY responded
1 - Port 23 PHY failed to respond
Default
0
17