ACD82124 Datasheet, PDF (15/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

Configuration Interface
There are 20 pins whose pull-up or pull-down state will
be used as Power-On-Strobing configuration data (Reg-
ister 25, & CFG0 - CFG19) to specify various working
modes of the ACD82124. The CFG pins are shared
with other functional pins of the ACD82124. The pull-
high or pull-low status of the CFG pins are used to
indicate specific configuration settings, described in
Table-6.11. The register description section will pro-
vide more details about the POS Configuration regis-
ter.
Table-6.11: Configuration Interface
Pin Name Register # Bit #
Setting
P7TXD0
0
P7TXD1
1
P7TXD2
2
P7TXD3
3
P6TXD0
4
P6TXD1
5
P6TXD2
6
P6TXD3
7
LEDCLK
LEDVLD0
25
LEDVLD1
8
See Table-
9
7.25
10
nLED3
11
nLED2
12
nLED1
13
nLED0
14
P5TXD0
15
P5TXD1
16
P5TXD2
17
P5TXD3
18
P2TxD0
0
P2TxD1
1
P2TxD2
2
P2TxD3
3
P3TxD0
4
P3TxD1
26
P3TxD2
5
See Table-
6
7.26
P3TxD3
7
P4TxD0
8
P4TxD1
9
P4TxD2
10
P4TxD3
11
P0TXD0
0
P0TXD1
1
P0TXD2
2
P0TXD3
P1TXD0
30
3
See Table-
4
7.30
P1TXD1
5
P1TXD2
6
P1TXD3
7
P23TXD0R
0 See Appendix-
P23TXD1R 20, inside the
1
A1
P23TXD2R Internal ARL
2
P23TXD3R
3
0
Other Interface (Table-6.12)
Table-6.12: Other Interface
Name
Type
Description
CLK50
I 50 MHz clock input
nRESET
I hardware reset
WCHDOG
O watch dog life pulse signal
VDD
- 3.3 V power
VSS
- ground
CLK50 should come from a clock oscillator, with 0.01%
(100 ppm) accuracy.
Assertion of the nRESET pin will cause the ACD82124
to go through the power-up initialization process. All
registers are set to their default value after reset.
When the ACD82124 is working properly, it will gener-
ate pulses from the WCHDOG pin continuously. It is
used as a safeguard, so that in case something unex-
pected happens, the external watchdog circuit will re-
set the switch system.
VDD is 3.3V power supply. VSS is power ground.
15