ACD82124 Datasheet, PDF (26/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

ERRMSK register (register 30)
The ERRMSK register defines certain errors as sys-
tem errors. It is reserved for factory use only. Table-
7.30 lists all the error masks specified by this register.
Table-7.30: ERRMSK register
Bit
Description
0
Reserved
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
Setting
All "1", unless
otherwise
advised, to
ensure proper
operation.
0
PHYREG registers (register 32-63)
The PHYREG refers to the registers residing on the
PHY devices. There are 24 sets of these registers.
Each port has its own corresponding set of register
32-63. The ACD82124 merely provides an access path
for the control CPU to access the registers on the
PHYs. For detailed information about these registers,
please refer to the PHY data sheet.
Since the native registers ID “0” through “31” on the
PHYs have been used by the internal registers of the
ACD82124, they need to be re-mapped into “32”
through “63” by adding “32” to each original register
ID. An index is used by the ACD82124 to specify the
PHY ID. For example, register-32 with index-4 would
refer to the control register (register-0) in the PHY-4.
CLKADJ register (register 31)
The CLKADJ register defines the delay time of the
ARLCLK relative to the transition edge of the data sig-
nals. The ARLCLK provides reference timing for sup-
porting chips, such as the ACD80800 and the
ACD80900, which need to snoop the data bus for cer-
tain activities. Table-7.31 describes all the bits of this
register.
Table-7.31: CLKADJ Register
Bit
Description
0
0 - ARLCLK not inverted
1 - ARLCLK inverted
3:1
ARLCLK delay levels:
000 - level 0 delay
001 - level 1 delay
010 - level 2 delay
011 - level 3 delay
100 - level 4 delay
101 - level 5 delay
110 - level 6 delay
111 - level 7 delay
Default
0
000
26