ACD82124 Datasheet, PDF (18/48 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch Controller

ACT register (register 5)
The ACT register indicates the presence of transmit or
receive activities of each port since the register was
last read. This register is automatically cleared after
each read. Table-7.5 describes all the bits of this reg-
ister.
SYSCFG register (register 16)
The SYSCFG register specifies certain system con-
figurations. The system options are described in the
chapter of “Function Description.” Table-7.16 describes
all the bit of this register.
Table-7.5: ACT Register
Bit
Description
0
0 - Port 0 no activity
1 - Port 0 has activity
1
0 - Port 1 no activity
1 - Port 1 has activity
2
0 - Port 2 no activity
1 - Port 2 has activity
3
0 - Port 3 no activity
1 - Port 3 has activity
4
0 - Port 4 no activity
1 - Port 4 has activity
5
0 - Port 5 no activity
1 - Port 5 has activity
6
0 - Port 6 no activity
1 - Port 6 has activity
7
0 - Port 7 no activity
1 - Port 7 has activity
8
0 - Port 8 no activity
1 - Port 8 has activity
9
0 - Port 9 no activity
1 - Port 9 has activity
10
0 - Port 10 no activity
1 - Port 10 has activity
11
0 - Port 11 no activity
1 - Port 11 has activity
12
0 - Port 12 no activity
1 - Port 12 has activity
13
0 - Port 13 no activity
1 - Port 13 has activity
14
0 - Port 14 no activity
1 - Port 14 has activity
15
0 - Port 15 no activity
1 - Port 15 has activity
16
0 - Port 16 no activity
1 - Port 16 has activity
17
0 - Port 17 no activity
1 - Port 17 has activity
18
0 - Port 18 no activity
1 - Port 18 has activity
19
0 - Port 19 no activity
1 - Port 19 has activity
20
0 - Port 20 no activity
1 - Port 20 has activity
21
0 - Port 21 no activity
1 - Port 21 has activity
22
0 - Port 22 no activity
1 - Port 22 has activity
23
0 - Port 23 no activity
1 - Port 23 has activity
Default
0
Table-7.16: SYSCFG Register
Bit
Description
Default
0 0 - BIST enabled;
0
1 - BIST disabled.
1 0 - Spanning Tree support disabled;
0
1 - Spanning Tree support enabled
2 Reserved.
0
3 Reserved.
0
4 Reserved.
0
5 0 - wait for CPU.
0
1 - system ready to start
*This bit is used by the CPU when bit-15 of
register-25 is set as "0" (for system with
control CPU). The system will wait for CPU
to set this bit.
6 0 - PHY Management not completed
0
1 - PHY Management completed.
*This bit is used by the CPU when bit-15 of
register-25 is set as "0" (for system with a
control CPU). The MAC will not start until this
bit is set sy the CPU.
7 0 - Watchdog function enabled.
0
1 - Watchdog function disabled.
8 0 - Secure VLAN checking rule enforced.
0
1 - Leaky VLAN checking rule enforced.
9 0 - Rising edge of RXCLK to latch data.
0
1 - Falling edge of RXCLK to latch data.
*For Reversed MII port only.
10 0 - Late Back-Pressure scheme disabled
0
1 - Late Back-Pressure scheme enabled
*When enabled, the MAC will generate back-
pressure only after reading the first bit of DA
11
0 - special handling of broadcast frames
disabled
0
1 - special handling of broadcast frames
enabled
*When enabled, all broadcast frames from
non-CPU port are forwarded to the CPU port
only, and all broadcast frames from the CPU
port are forwarded to all other ports.
12 ^{Software Reset: "1" to start a system reset to} 0
innitialize all state machines.
Hardware Reset: "1" to stop the life pulse on
13 ^{the watchdog pin, which in turn will trigger the}
external watchdog circuitry to reset the whole
system.
14 Reserved
0
15 Reserved
0
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