MB8117800A-60 Datasheet, PDF (6/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

MB8117800A-60/-70
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DATA OUTPUTS
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following
conditions:
tRAC :
tCAC :
tAA :
tOEA :
from the falling edge of RAS when tRCD (max) is satisfied.
from the falling edge of CAS when tRCD is greater than tRCD (max).
from column address input when tRAD is greater than tRAD (max).
from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA.
The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the
output buffers remain in a high-impedance state during the entire cycle.
FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page
mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy
these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For
each fast page of memory, any of 1,024 x 8-bits can be accessed and, when multiple MB8117800As are used,
CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed
sequentially and combinations of read, write, and/or read-modify-write cycles are permitted.
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