MB8117800A-60 Datasheet, PDF (15/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

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MB8117800A-60/-70
Fig. 7 – DELAYED WRITE CYCLE
tRC
tRAS
VIH
tAR
RAS _VIL
tRP
tCSH
tCRP
tRCD
tCAS
tRSH
VIH
CAS
VIL
tASR tRAH
tASC
tCAH
A0 to A10 ^VIH
VIL
VIH
WE
VIL
DQ ^VIH
(Input) VIL
DQ ^VOH
(Output) VOL
VIH
OE
VIL
COL
ADD
COL
ADD
tRCS
tWCH
tCWL
tWP
tRWL
tDZC
HIGH-Z
HIGH-Z
tDZO
tDS
tOED
tON
tDH
VALID
DATA IN
tON
tOEZ
tOEH
HIGH-Z
“H” or “L”
Invalid Data
DESCRIPTION
In the delayed write cycle, tWCS is not satisfied; thus, the data on the DQ pins is latched with the falling edge of WE and written into
memory. The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED + tDS).
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