MB8117800A-60 Datasheet, PDF (14/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

MB8117800A-60/-70
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VIH
RAS
VIL
VIH
CAS
VIL
A0 to A10 ^VIH
VIL
VIH
WE
VIL
DQ ^VIH
(Input) VIL
DQ ^VOH
(Output) VOL
Fig. 6 – EARLY WRITE CYCLE (OE = “H” or “L”)
tRC
tRAS
tCRP
tCSH
tRP
tRCD
tRSH
tCAS
tASR
tAR
tRAH
tASC
tCAH
ROW ADD
COLUMN ADD
tWCS
tWCR
tWCH
tDHR
tDS
tDH
VALID DATA IN
HIGH-Z
“H” or “L”
DESCRIPTION
A write cycle is similar to a read cycle except WE is set to a Low state and OE is an “H” or “L” signal. A write cycle can be imple-
mented in either of three ways - early write, delayed write or read-modify-write. During all write cycles, timing parameters tRWL, tCWL,
and tRAL must be satisfied. In the early write cycle shown above tWCS satisfied, data on the DQ pin is latched with the falling edge of
CAS and written into memory.
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