MB8117800A-60 Datasheet, PDF (19/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

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MB8117800A-60/-70
Fig. 11 – FAST PAGE MODE DELAYED WRITE CYCLE
VIH
RAS _VIL
tRASP
tCPR
tRCD
tCSH
tCAS
tPC
tCP
tRSH
tRP
VIH
CAS _VIL
tASR
tRAH
tAR
tASC
tCAH
tASC
tCAS
tCAH tCWL
A0 to A10 ^VIH
VIL
ROW
ADD
COL
ADD
COL
ADD
VIH
WE
VIL
DQ VIH
(Input) _VIL
tRCS
tWCH
tWP
tCWL
tDZC
tOED
tON
tDS
tDH
VALID
tOEH
tON
tWCH
tRWL
tWP
tDS
tDH
VALID
tOED
DQ VOH
(Output) _VOL
VIH
OE
VIL
tON
tDZO
tON
tOEZ
tOEH
tOEZ
“H” or “ L”
Valid Data
DESCRIPTION
The fast page mode delayed write cycle is executed in the same manner as the fast page mode early write cycle except for the states
of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the fast page mode
delayed write cycle, OE must me changed from Low to High before WE goes Low (tOED + tT + tDS).
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