MB8117800A-60 Datasheet, PDF (24/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

MB8117800A-60/-70
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Fig. 17 – SELF REFRESH CYCLE (A0-A10 = WE = OE = “H” or “L”)
VIH
RAS _VIL
VIH
CAS
VIL
DQ ^VOH
(Output) VOL
tCPN
tOFF
tOH
tCSR
tRASS
tRPS
tCHS
tRPC
HIGH-Z
“H” or “L”
A0 to A10, WE, OE = “H” or “L”
No.
100
101
102
(At recommended operating conditions unless otherwise noted.)
Parameter
RAS Pulse Width
RAS Precharge Time
Symbol
tRASS
tRPS
MB817800A-60
Min.
Max.
100
—
110
—
MB817800A-70 _Unit
Min.
Max.
100
—
µs
125
—
ns
CAS Hold Time
tCHS
–50
—
–50
—
ns
DESCRIPTION
Note: Assumes self refresh cycle only
The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip
is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter and
timing generator. If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of tRASS
(more than 100 µs), the device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed
intervals using internal refresh address counter during “RAS = L” and “CAS = L”.
Exit from self refresh cycle is performed by togging RAS and CAS to “H” with specified tCHS min.. In this time, RAS must be kept “H”
with specified tRPS min..
Using self refresh mode, data can be retained without external CAS signal during system is in standby.
Restriction for Self Refresh operation;
For self refresh operation, the notice below must be considered.
1) In the case that distributed CBR refresh are operated between read/write cycles
Self refresh cycles can be executed without special rule if 2,048 cycles of distributed CBR refresh are executed
within tREF max..
2) In the case that burst CBR refresh or distributed burst RAS-only refresh are operated between read/write cycles
2,048 times of burst CBR refresh or 2,048 times of burst RAS-only refresh must be executed before and after
Self refresh cycles.
RAS ^VIH
VIL
24
Read/Write operation
Self Refresh operation
tRASS
Read/Write operation
tNS < 2 ms
2,048 burst refresh cycle
tSN < 2 ms
*
2,048 burst refresh cycle
*
* read/write operation can be performed non refresh time within tNS or tSN