MB8117800A-60 Datasheet, PDF (13/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM

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MB8117800A-60/-70
VIH
RAS _VIL
VIH
CAS
VIL
A0 to A10 ^VIH
VIL
VIH
WE
VIL
DQ ^VOH
(Output) VOL
DQ ^VIH
(Input) VIL
VIH
OE
VIL
Fig. 5 – READ CYCLE
tRC
tRAS
tAR
tCRP
tRCD
tRAD
tASR
tRAH
tASC
tCSH
tRSH
tCAS
tCAH
tRAL
tCAL
ROW ADD
COLUMN ADD
tRCS
HIGH-Z
tDZC
tRAC
tAA
tCAC
tON
tOEA
HIGH-Z
tDZO
tRP
tOEL
tCDD
tRRH
tRCH
tOH
tOFF
tOEZ
tOH
tON
tOED
“H” or “L”
DESCRIPTION
To implement a read operation, a valid address is latched in by the RAS and CAS address strobes and with WE set to a High level
and OE set to a low level, the output is valid once the memory access time has elapsed. The access time is determined by RAS(tRAC),
CAS(tCAC), OE(tOEA) or column addresses (tAA) under the following conditions:
If tRCD > tRCD (max), access time = tCAC.
If tRAD > tRAD (max), access time = tAA.
If OE is brought Low after tRAC, tCAC, or tAA(whichever occurs later), access time = tOEA.
However, if either CAS or OE goes High, the output returns to a high-impedance state after tOH is satisfied.
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