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MB8117800A-60 Datasheet, PDF (21/27 Pages) List of Unclassifed Manufacturers – 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM | |||
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MB8117800A-60/-70
Fig. 13 â RAS-ONLY REFRESH (WE = OE = âHâ or âLâ)
VIH
RAS VIL
A0 to A10 VIH
VIL
VIH
CAS
VIL
tRAS
tASR
tRAH
ROW ADDRESS
tCRP
tOFF
tRC
tRPC
tRP
tCRP
tOH
DQ VOH
(Output) VOL
DESCRIPTION
HIGH-Z
âHâ or âLâ
Referesh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row
addresses every 32.8-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden
refresh.
RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched
on the falling edge of RAS. During RAS-only refresh, DOUT pins are kept in a high-impedance state.
Fig. 14 â CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = âHâ or âLâ)
VIH
RAS VIL
VIH
CAS
VIL
DQ VOH
(Output) VOL
tCPN
tCSR
tCHR
tRC
tRP
tRAS
tRPC
tOFF
tOH
HIGH-Z
âHâ or âLâ
DESCRIPTION
CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low
for the specified setup time (tCSR) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter
are enabled. An internal refresh operating automatically occurs and the refresh address counter is internally incremented in prepa-
ration for the next CAS-before-RAS refresh operation.
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