82C931 Datasheet, PDF (51/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
Table 5-10 Codec Indirect Registers (cont.)
D7
D6
D5
D4
D3
D2
D1
D0
CIR15
Playback Lower Base Count Register
Default = 00h
Lower Base Count:
This byte is the lower byte of the base count register containing the eight least significant bits of the 16-bit base register.
Reads from this register return the same value which was written The current count contained in the counters can not be read.
When enabled for SD Mode, this register is used for both the Playback and Capture Base Registers.
Table 5-11 Expanded Mode CIR
7
6
5
4
3
2
1
CIR16
Mute:
0 = Disable
1 = Enable
Reserved
AUXL Input Control Register
Gain select for AUXL (dB):
Refer to CIR2[4:1] for decode.
CIR17
Mute:
0 = Disable
1 = Enable
Reserved
AUXR Input Control Register
Gain select for AUXR (dB):
Refer to CIR2[4:1] for decode.
CIR18
Mute:
0 = Disable
1 = Enable
Reserved
LINEL Input Control Register
Gain select for LINEL (dB):
Refer to CIR2[4:1] for decode.
CIR19
Mute:
0 = Disable
1 = Enable
Reserved
LINER Input Control Register
Gain select for LINER inputs (dB):
Refer to CIR2[4:1] for decode.
CIR20
Mute:
0 = Disable
1 = Enable
MICR mixed
into OUTL:
0 = Disable
1 = Enable
Reserved
MICL Input Control Register
Gain select for MICL (dB):
Refer to CIR2[4:1] for decode.
CIR21
Mute:
0 = Disable
1 = Enable
MICL mixed
into OUTR:
0 = Disable
1 = Enable
Reserved
MICR Input Control Register
Gain select for MICR (dB):
Refer to CIR2[4:1] for decode.
0
Default = 88h
Reserved
Default = 88h
Reserved
Default = 88h
Reserved
Default = 88h
Reserved
Default = 88h
Reserved
Default = 88h
Reserved
912-3000-035
Revision: 2.1
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