82C931 Datasheet, PDF (46/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
Note that at the Codec Index Address Register
(WSBase+04h), bits 4 through 0 are used as the index
address for accessing the Codec Indirect Registers (CIR). A
write to or a read from the Codec Indexed Data Register
(WSBase+05h) will access the Indirect Register which is
indexed by the value most recently written to the Codec Index
Address Register.
There are 31 Codec Indirect Registers, CIR0-CIR15 are
accessed normally. To access CIR16 through CIR31,
Expanded Mode registers, MCIR12[5] = 1 (MCBase Indirect
Register, bit 5). Table 5-10 gives the bit formats for CIR0-
CIR15 and Table 5-11 shows CIR16-CIR31.
Table 5-9 WSBase Register for Codec/Mixer Applications
7
6
5
4
3
2
1
0
WSBase+04h
Codec Index Address Register (R/W, exists in Codec and shadowed in 82C931)
Default = 00h
Initialization:
This bit is set
when the
codec is in a
state which can-
not respond to
parallel bus
cycles.⁽¹⁾
Mode change:
0 = Disable
1 = Enable
Transfer
request:⁽²⁾
0 = Transfers
enabled during
interrupt
1 = Transfers
disabled by
interrupt
Index address:
These bits specify which Codec Indirect Register (CIR) is to be accessed.
Note CIR16 through CIR31 are Expanded Modes and require that MCIR12[5] = 1.
(Refer to Table 5-10 and Table 5-11 for these registers bit formats.)
00000 = CIR0: MIXOUTL Output Cntrl
00001 = CIR1: MIXOUTR Output Cntrl
00010 = CIR2: CDL Input Cntrl
00011 = CIR3: CDR Input Cntrl
00100 = CIR4: FML Input Cntrl
00101 = CIR5: FMR Input Cntrl
00110 = CIR6: DACL Input Cntrl
00111 = CIR7: DACR Input Cntrl
01000 = CIR8: Fs & Playback Data Format
01001 = CIR9: Interface Configuration
01010 = CIR10: Pin Cntrl
01011 = CIR11: Error Status & Initialization
01100 = CIR12: Mode and ID (Mode 2 Bit)
01101 = CIR13: Reserved
01110 = CIR14: Playback Upper Base
01111 = CIR15: Playback Lower Base
Expanded Mode Registers
10000 = CIR16: AUXL Input Cntrl
10001 = CIR17: AUXR Input Cntrl
10010 = CIR18: LINEL Input Cntrl
10011 = CIR19: LINER Input Cntrl
10100 = CIR20: MICL Input Cntrl
10101 = CIR21: MICR Input Cntrl
10110 = CIR22: OUTL Gain Cntrl
10111 = CIR23: OUTR Gain Cntrl
11000 = CIR24: Reserved
11001 = CIR25: Reserved
11010 = CIR26: Reserved
11011 = CIR27: Reserved
11100 = CIR28: Capture Data Format
11101 = CIR29: Reserved
11110 = CIR30: Capture Upper Base
11111 = CIR31: Capture Lower Base
(1) Immediately after reset and once the codec has left the initialization state, the initial value of this register will be "0100 0000" (40h). During
codec initialization, the Codec Index Register cannot be written and is always read 1000 0000 (80h).
(2) When bit 5 is set, DMA transfers cease when bit 0 of the Codec Status Register (WSBase+06h) = 1.
WSBase+05h
Codec Indexed Data Register (R/W, exists in Codec only)
Contains the contents of the Codec register referenced by the Index Data Register.
During codec initialization, this register cannot be written and is always read as "1000 0000" (80h).
Default = 00h
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Revision: 2.1