82C931 Datasheet, PDF (50/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
Table 5-10
D7
CIR10
Codec Indirect Registers (cont.)
D6
D5
D4
D3
Pin Control Register
Reserved
2. In Sound Blaster mode, the software driver should set bit 1 = 1.
D2
D1
D0
Interrupt pin:⁽¹⁾
0 = Disable
1 = Enable
(Interrupt pin
goes active high
when the num-
ber of samples
programmed in
the Base Count
Register is
reached.)
Default = 00h
Reserved
CIR11
Error Status and Initialization Register (RO)
Default = 00h
Capture
overrun:⁽¹⁾
This bit is set
when capture
data has not
been read by
the host before
the next sam-
ple arrives. The
sample being
read will not be
overwritten by
the new sam-
ple. The new
sample is
ignored.
Playback
underrun:⁽¹⁾
This bit is set
when playback
data has not
arrived from
the host in time
to be played.
This results in a
midscale value
sent to the
DACs.
Autocalibration
state:
0 = In progress
1 = Not in
progress
Current status Indicates under/over range on
of PDRQ and
CDRQ:
0 = Inactive
(low)
right input channel:⁽¹⁾
0 = Less than –1dB under range
1 = Between –1dB and 0dB under
range
1 = Active (high) _{2 = Between 0dB and +1dB over}
range
Indicates under/over range on
left input channel:⁽¹⁾
0 = Less than –1dB under range
1 = Between –1dB and 0dB under
range
2 = Between 0dB and +1dB over
range
3 = Greater than +1dB over range 3 = Greater than +1dB over range
(1) Bit changes on a sample-by-sample basis.
(2) The occurrence of a capture overrun and/or playback underrun is designated in the Status Register's sample overrun/underrun bit
(WSBase+06h[4]). The sample overrun/underrun bit is the logical OR of bits 7 and 6. This enables a polling host CPU to detect an over-
run/underrun condition while checking other status bits.
CIR12
Reserved
ID Register
Default = 0Ah
Revision ID (RO):
These bits define the revision level of the codec.
CIR13
Reserved
Default = 00h
CIR14
Playback Upper Base Count Register
Default = 00h
Upper Base Count:
This byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register.
Reads from this register return the same value which was written The current count contained in the counters can not be read.
When enabled for SB Mode, this register is used for both the Playback and Capture Base Registers.
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