82C931 Datasheet, PDF (49/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
Table 5-10 Codec Indirect Registers (cont.)
D7
D6
D5
D4
D3
D2
D1
CIR6
Mute:
0 = Disable
1 = Enable
Reserved
DACL Input Control Register
Gain select for DAC inputs (dB):
*00000 = 0
00001 = –1.5
00010 = –3.0
00011 = –4.5
00100 = –6.0
00101 = –7.5
00110 = –9.0
00111 = –10.5
01000 = –12.0
01001 = –13.5
01010 = –15.0
01011 = –16.5
01100 = –18.0
01101 = –19.5
01110 = –21.0
01111 = –22.5
10000 = –24.0
10001 = –25.5
10010 = –27.0
10011 = –28.5
10100 = –30.0
10101 = –31.5
10110 = –33.0
10111 = –34.5
D0
Default = 80h
11000 = –36.0
11001 = –37.5
11010 = –39.0
11011 = –40.5
11100 = –42.0
11101 = –43.5
11110 = –45.0
11111 = –46.5
CIR7
Mute:
0 = Disable
1 = Enable
Reserved
DACR Input Control Register
Gain select for DAC inputs (dB):
Refer to CIR6[4:0] for decode.
Default = 80h
CIR8
Fs and Playback Data Format Register
Default = 00h
Audio data format - linear PCM or companded
for all input and output data
(used in conjunction with bit 5):⁽¹⁾
000 = Linear, 8-bit unsigned
001 = µ-law, 8-bit companded
010 = Linear, 16-bit two’s complement, Little Endian
011 = A-Law, 8-bit companded
100 = Reserved
101 = ADPCM, 4-bit, IMA compatible
110 = Linear, 16-bit two’s complement, Big Endian
111 = Reserved
Stereo/mono:⁽²⁾
0 = Mono
1 = Stereo
Clock frequency divide / audio sample
rate frequency:
0000 = 8.0kHz
0010 = 16.0kHz
0001 = 5.5125kHz
0011 = 11.025kHz
0100 = 27.42857kHz
0110 = 32.0kHz
1000 = Reserved
1010 = Reserved
0101 = 18.9kHz
0111 = 22.05kHz
1001 = 37.8kHz
1011 = 44.1kHz
1100 = 48.0kHz
1110 = 9.6kHz
1101 = 33.075kHz
1111 = 6.615kHz
Note: Bit 7 is not available in Mode 1 (forced to 0).
(1) SB/WSS mode switch: In Sound Blaster mode, the software driver should set CDF to 8 bit PCM mode (R8: FM1,FM-,C_L).
(2) Selecting stereo results with alternating samples representing left and right audio channels. Mono playback plays the same audio sample
on both channels. Mono capture only captures data from the left audio channel.
Note: The contents of this register can only be changed if the mode change bit (WSBase+04h[6]) is enabled (set to 1). Writes to this register
without the mode change bit enabled will have no affect.
CIR9
Interface Configuration Register
Default = 00h
Transfer cap-
ture data via
DMA or PIO:
0 = DMA
1 = PIO
Transfer play-
back data via
DMA or PIO:
0 = DMA
1 = PIO
Reserved
Autocalibrate:
0 = Disable
1 = Enable
(autocalibration
after power
down/reset or
mode change
DMA channel
mode:⁽¹⁾
0 = Dual
1 = Single
Capture data in
format
selected:⁽²⁾
0 = Disable
1 = Enable
Playback data
in format
selected:⁽³⁾
0 = Disable
1 = Enable
(1) In Sound Blaster mode, bit 2 is set when playback or capture DMA starts and is reset when DMA ends.
(2) The codec generates CDRQ and responds to CDAK# when bit 1 = 1 and bit 7 = 0. If bit 7 = 1, bit 1 enables PIO capture mode.
(3) The codec generates PDRQ and repents to PDAK# when bit 0 = 1 and bit 6 = 0. If bit 6 = 1, bit 1 enables PIO playback mode
912-3000-035
Revision: 2.1
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