82C931 Datasheet, PDF (33/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
Bit 3
Bit 2
Bit 1
Bit 0
SCLK polarity:
0:
SDATA and LRCLK change at the rising edge of SCLK
1:
SDATA and LRCLK change at the falling edge of SCLK
FSYNC (LRCLK) polarity:
0:
LRCLK is LOW for the left channel, HIGH for the right channel
1:
LRCLK is HIGH for the left channel, LOW for the right channel
Pulse mode: Used for AT&T T7525 codec or CS8412 DSP data format
0:
Pulse mode disabled
1:
Pulse mode enabled, used for AT&T T7525 or CS8412 data format
I²S mode: MSB delay mode
0:
Zero SCLK delay from an LRCLK transition to MSB data
1:
One SCLK delay from an LRCLK transition to MSB data
MC21 Serial Audio selection control register (R/W)
bit 7
bit 6
CTL_SEL[1:0]
bit 5
bit 4
P2S_SEL[1:0]
bit 3
SPCDSEL
bit 2
ADCSEL
bit 1
FDACSEL
bit [7:6] CTL_SEL[1:0]: ASIO shift clock selection
00/11: Use the shift clock from internal FS
01:
Use FM timing
10:
Use external SCLK
bit 1 FDACSEL: selects the data source to the FDAC
0:
FDAC takes FM data
1:
FDAC takes SADI (if SPCDSEL=0) or second DMA playback data (if SPCDSEL=1)
Default: 00h
bit 0
DACSEL
4.8.6 ZV-Port I²S
4.8.6.1 LRCLK
This signal determines which audio channel (left/right) is cur-
rently being input on the audio Serial Data input line. LRCLK
is low to indicate the left channel and high to indicate the right
channel. Typical frequency values for this signal are 48KHz,
44.1KHz, 32KHz, and 22KHz.
4.8.6.2 SDATA
This signal is the digital PCM signal that carries the audio
information. Digital audio data is transferred using the I²S for-
mat.
I²S Format
The I²S format is shown below. The digital audio data is left
channel-MSB justified to the high-to-low going edge of the
LRCLK plus one SCLK delay.
Figure 4-3 I²S Format
LRCLK
SCLK
SDATA
Left Channel
Right Channel
15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0
912-3000-035
Revision: 2.1
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