82C931 Datasheet, PDF (45/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
Table 5-7 SBBase Registers for FM and DAP Applications (cont.)
7
6
5
4
3
2
1
0
SBBase+0Eh
DAP Output Buffer Status Register (RO
DAP output
buffer is full:⁽¹⁾
Output Buffer
0 = Empty
1 = Full
(1) This flag is set in the DAP when data is written in the output data bus buffer and cleared when the host CPU or the DMA controller reads
the data in the output data bus buffer.
Note: Reading this register will also clear the Digital Audio Processor interrupt request.
5.4 WSBase Register
Two types of registers can be accessed through WSBase:
• Windows Sound System (WSS) and Codec registers
These registers are accessed through the WSBase register
and use the same type of indexing scheme as MCBase (CPU
Direct I/O R/W). The bit formats for WSS-related registers are
given in Table 5-8 and Table 5-9 shows the Codec-related
registers.
Table 5-8 WSBase Registers for Windows Sound System Applications
7
6
5
4
3
2
WSBase+00h-03h
Reserved
IRQ sense
source:
0 = Normal
1 = auto-inter-
rupt selection
WSS Configuration Register (W0)
WSS IRQ select:
000 = Disable
001 = IRQ7
010 = IRQ9
011 = IRQ10
100 = IRQ11
101 = IRQ5
110 = Reserved
111 = Reserved
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
1
0
Default = 00h
WSS DRQ select:
Playback
Disable
DRQ0
DRQ1
DRQ3
Disabled
DRQ0
DRQ1
DRQ3
Capture
Disable
Disable
Disable
Disable
DRQ1
DRQ1
DRQ0
DRQ0
WSBase+00h-03h
Channel
available:
0 = DRQ0/1/3
and
IRQ7/9/10/
11 available
IRQ sense:
0 = No interrupt
1 = WSS inter-
rupt active
1 = DRQ1/3 and
IRQ7/9
available
WSS Version Register (R0)
Version: 04h
Default = 00h
912-3000-035
Revision: 2.1
OPTi
®
Page 37