82C931 Datasheet, PDF (32/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
To program the 931 in the I²S-justified mode, the MC22 and
MC21 registers need to be set. The relevant MC22 and
MC21 bit definitions are shown below for reference.
I²S-justified mode (ZV-port):
MC22[7:0] = "00110001" (31H).
MC21[7:0] = "10000010" (82H).
There are other I²S variations: left-justified and right-justified.
For the left-justified, LRCLK is high for the left channel, and
low for the right channel. The MSB is left-justified to an
LRCLK transition, with zero SCLK delay.
MC22[7:0] = "00110100" (34H).
MC21[7:0] = "10000010" (82H).
For the right-justified, LRCLK is high for the left channel, and
low for the right channel. The MSB is delayed from an LRCLK
transition, the LSB will be right-justified to the next LRCLK
transition.
MC22[7:0] = "00010100" (14H).
MC21[7:0] = "10000010" (82H).
4.8.2 Sony format¹
This data format is essentially the same as the I²S right-justi-
fied format. Normally there are only 32 SCLKs in a LRCLK
period. The LRCLK is high for the left channel, and low for the
right channel. The MSB comes in first. To set up the 931 in
Sony format:
MC22[7:0] = "00000100" (04H).
MC21[7:0] = "10000010" (82H).
4.8.3 AT&T PCM codec T7525 compatible 16-bit
mono format
The 931 supports the T7525 receive timing - word format with
positive FSYNC. The benefit is that the 931's secondary DAC
could be used to save a T7525 as the voice codec in
modem/audio combo solution. To program the 931 in T7525
mode:
MC22[7:0] = "00110010" (32H)
MC21[7:0] = "10000010" (82H)
In short summary:
MC22[7:0]
MC22[7:0]
I²S-
justified
31H*
left-
justified
34H*
right-
justified
14H*
82H
Sony
format
04H*
T7525
format
32H
* The MC22[4] bit setting may vary, depending on the LRCLK
period (32 SCLK or more).
4.8.4 Testing I²S format (ZV port) with Audio Pre-
cision machine
The Audio Precision machine system two 2322 has a serial
audio data port that can generate a test tone in the I²S format
with programmable FSYNC, ranging from 24KHz to 48KHz.
The 931 was tested with AP machine in various test tones:
256Hz, 1KHz and 3KHz in both sine wave and square wave
with FSYNC = 48KHz.
To test out the feature, the AP machine is hooked up with the
931 with appropriate connections (AP's pin#6, 12, 14 are
SDATA, SCLK and FSYNC, respectively). The next step is to
setup the MC22 to “31H” and MC21 to “82H”. Then the test
tone could be heard from the speaker connected to the 931.
Please note that there might be some noise in the speaker.
This is due to unshielded cable used to connect the serial
audio interface. Shielding the cable would help improve the
audio quality.
4.8.5 Relevant MC register settings
MC22 Serial Audio format control register (R/W)
Default: 00h
bit 7
Reset ASIO
bit 6
ASIO test
enable
bit 5
First16-bit
bit 4
CLK32
bit 3
SCLK
Polarity
bit 2
FSYNC
Polarity
bit 1
Pulse Mode
bit 0
I²S Mode
Bit 5
Bit 4
First16-bit: Specifies where the data is located in the LRCLK period
0:
data located at the last 16 bits of the left/right channel in an LRCLK period
1:
data located at the first 16 (or 17) bit of the left/right channel in an LRCLK period
CLK32: Specifies the number of SCLKs per LRCLK period, used only in delay-mode or pulse-mode ASIO
0:
32 SCLK per LRCLK period
1:
more than 32 SCLK per LRCLK period
1. Short right-justified format, used by OPTi's wavetable chip and the Philips TDA1311AT DAC.
OPTi
®
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Revision: 2.1