82C931 Datasheet, PDF (39/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
Table 5-6 MC Indirect Registers
7
6
5
4
3
2
1
MCIR1
Sound Blaster
I/O base
address
(SBBase):
0 = 220
1 = 240
Reserved
Base/Type Configuration Register
Windows Sound System I/O base
address (WSBase):
00 = 530
10 = F40
01 = E80
11 = 640
CD-ROM interface:
The sense of these bits is reversed during writes.
To disable CD, write b’011’.
000 = Disabled
100 = Secondary IDE
All others = Reserved
0
Default = 06h
Game port:
0 = Disable
1 = Enable
MCIR2
Reserved
Set to 0.
BAUD 96 register
BAUD96:
This bit could
be used by PDA
devices to com-
municate with
other devices
0 = Disabled,
normal MIDI
UART in RXD
pin.
1 = Enabled,
9600 baud rate
UART in RXD
pin
Reserved
Set to 0.
Default = 00h
MCIR3
Sound Blaster/Windows Sound System Configuration Register
Default = 00h
Reserved:
Must be set to
0.
Reserved:
Must be set to 0
for normal oper-
ation in WSS.
DAP IRQ select:
000 = Disable
001 = IRQ7
010 = IRQ9
011 = IRQ10
100 = IRQ11
101 = IRQ5
110 = Reserved
111 = Reserved
(1) If CIR9[2] = 0 (Codec Indirect Register 9, bit 2), then DAP DMA[4:7] can be selected
DAP DMA select:
000 = Disabled
001 = DRQ0
010 = DRQ1
011 = DRQ3
100 = Disable DRQ1⁽¹⁾
101 = DRQ0 DRQ1⁽¹⁾
110 = DRQ1 DRQ0⁽¹⁾
111 = DRQ3 DRQ0⁽¹⁾
MCIR4
User Programmable General Purpose Register
Playback FIFO flow control:
00 = Empty 10 = Full-4
01 = Full-2 11 = Not full
OPL select:
00 = OPL2 10 = OPL4
01 = OPL3 11 = OPL5
Digital-Analog
controller zero:
0 = Hold
1 = Clear
(1) Bit 2 can also accessed through the MC register or through PNP logic.
Audio:⁽¹⁾
0 = Disable
1 = Enable
Default = 10h
Sound Blaster version:
00 = 2.1
01 = 1.5
10 = 3.2
11 = 4.4
MCIR5
Option Register
Default = 00h
Reserved
Codec
Expanded
Mode:⁽¹⁾
0 = Disable
1 = Enable
Sound Blaster
ADPCM:
0 = Disable
1 = Enable
Command FIFO
in Sound
Blaster mode:
0 = Disable
1 = Enable
Volume effect
for Sound
Blaster Pro
mixer voice vol-
ume emulation:
0 = Disable
1 = Enable
DMA watch
dog timer:
0 = Disable
1 = Enable
When enabled,
the 82C931 will
generate inter-
nal DACK after
the DRQ pend-
ing time-up.
Reserved
(1) Bit 5 must be set in order to access the CIR16-31, the Expanded Mode of the Codec Indirect Registers. Refer to Table 5-9 and Table 5-11.
912-3000-035
Revision: 2.1
OPTi
®
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