82C931 Datasheet, PDF (34/64 Pages) List of Unclassifed Manufacturers – Plug and Play Integrated Audio Controller

82C931
4.8.6.3 SCLK
This signal is the serial digital audio PCM clock.
4.8.6.4 MCLK
This signal is the Master clock for the digital audio. MCLK is
asynchronous to LRCLK, SDATA and SCLK.
The MCLK must be either 256x or 384x the desired Input
Word Rate (IWR). IWR is the frequency at which words for
each channel are input to the DAC and is equal to the LRCLK
frequency. The following table illustrates several standard
audio word rates and the required MCLK and LRCLK fre-
quencies. Typically, most devices operate with 384fx master
clock.
The ZV Port audio DAC should support an MCLK frequency
of 384fs. This results in the frequencies shown below.
LRCLK (KHz)
Sample Frequency
22
32
44.1
48
SCLK (MHz)
32xfs
0.704
1.0240
1.4112
1.5360
MCLK (MHz)
384x
8.448
12.2880
16.9344
18.4320
4.8.7 Advanced Precision General Purpose
Serial Port
The 15-pin "D-sub" connector on the rear panel provides all
input and output signals for a general purpose serial
input.output port, plus DSP-program specific input and output
pins which may be used in certain DSP (.AZ2) programs. The
pinout of the connector is detailed below. All inputs are TTL
level compatible CMOS. All outputs are CMOS isolated by
50Ω series resistors and rise time limiting networks.
Pin Function
1 Ground
2 +5V (tied to unused
inputs high)
3 Auxiliary Input (DSP
program specific)
4 Ground
5 Ground
6 Serial Output Data
(output)
7 Ground
8 Ground
Pin Function
9 Serial Input Master
Clock (input)
10 Serial Input Bit Clock
(input)
11 Auxiliary Output (DSP
program specific)
12 Serial Output Bit
Clock (output)
13 Serial Input Data
(input)
14 Serial Output Frame
Sync (output)
15 Serial Input Frame
Sync (input)
Figure 4-4 General Purpose Serial Port, Timing Relationships
MSB
Bit Clock In
MSB
Data In
Frame Sync In
CHAN
A
LSB
Channel A
MSB
LSB
MSB
LSB
MSB
Channel B
CHAN
A
CLK
CLK
63
0
CLK
1
CLK
2
Detail
Detail
Bit Clock In
CLK
31
CLK
CLK
CLK
32
33
34
CH A
MSB
34
12
Data In
Frame Sync In
CH B
MSB
34
12
1. FRAME SYNC INPUT SETUP TIME (from falling edge, las bit clock previous subframe) 30nS minimum
2. FRAME SYNC INPUT SETUP TIME (to falling edge, first bit clock of present subframe) 30nS minimum
3. DATA INPUT SETUP TIME (to bit clock falling edge) 30nS minimum
4. DATA INPUT HOLD TIME (from bit clock falling edge) 45nS minimum
OPTi
®
Page 26
912-3000-035
Revision: 2.1