STC4130 Datasheet, PDF (4/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

STC4130 Pin Description
STC4130
Synchronous Clock for SETS
Data Sheet
Table 1: Pin Description
Pin Name
Vdd33
Vdd18
Vss
AVdd18
Avss
TRST
TCK
TMS
TDI
TDO
RESET
MCLK
MCLK_FRQ_SEL
BUS_MODE0
BUS_MODE1
BUS_CS
BUS_ALE
BUS_WRB
BUS_RDB
BUS_RDY
BUS_A6
BUS_A5
BUS_A4
BUS_A3
BUS_A2
BUS_A1
BUS_A0
BUS_AD7
Pin #
I/O¹
Description
6,22,31,
44,59,
69,80,
89,97
I 3.3V power input
9,18,27,
I 1.8V power input
38,47,53,
65,73,84,
92
3,13,15,
20,29,35,
41,49,56,
62,67,71,
78,82,87,
95
Digital ground
1, 76
1.8V analog power input
75, 100
Analog ground
94
I JTAG reset
93
I JTAG clock
91
I JTAG mode selection
90
I JTAG data input
88
O JTAG data output
30
I Active low to reset the chip
99
I Master clock input, 10 MHZ or 20 MHz
98
I Master clock frequency select, 0 = 10 MHz or 1 = 20 MHz
63
I Bus mode selection, 00: SPI, 01: Motorola, 10: Intel, 11: Multiplex
64
I Bus mode selection, 00: SPI, 01: Motorola, 10: Intel, 11: Multiplex
45
I Parallel bus or SPI Chip select
46
I Parallel bus address latch or SPI clock input
48
I Parallel bus write or SPI data input
50
I Parallel bus read or read/write input
51
O Parallel bus ready output or SPI data output
61
I Bus Address bit 6
60
I Bus Address bit 5
58
I Bus Address bit 4
57
I Bus Address bit 3
55
I Bus Address bit 2
54
I Bus Address bit 1
52
I Bus Address bit 0
43
I/O Parallel bus address/data bit7
Data Sheet #: TM084 Page 4 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice