STC4130 Datasheet, PDF(12/44 Page) List of Unclassifed Manufacturers

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STC4130 Datasheet, PDF (12/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

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select the (T0/T4)_XSYNC_IN cross-couple Syn-

cLinkTM data link(s) as the source of phase informa-

tion.

STC4130

Synchronous Clock for SETS

Data Sheet

In master mode, the T0 and T4 clock generators may

each operate in the Freerun, Synchronized, or Hold-

over modes:

1. Free Run

In freerun mode, the CLK(0-7) clock outputs are

determined directly from and have the accuracy of

the digitally calibrated free running OCXO/TCXO.

Reference inputs continue to be monitored for signal

presence and frequency offset, but are not used to

synchronize the outputs.

Freerun

No Reference

Available and

HO not Available

Any

Reference

Available

Locking

Active Reference

not available or

higher priority

reference is

available in

revertive mode

Frequency

Locked

2. Synchronized

The CLK(0-7) clock outputs are phase locked to and

track the selected input reference. Upon entering the

Locking mode, the device begins an acquisition pro-

cess that includes reference qualification and fre-

quency slew rate limiting, if needed. Once

satisfactory lock is achieved, the âLockedâ state is

entered, and the âSYNCâ bit is set in the T(0/

4)_DPLL_Status register.

Locked

Synchronized

No Reference Available

and HO Available

Any

Reference

Available

Holdover

Each DPLLâs loop bandwidth may be set indepen-

dently. Loop bandwidth is selectable from 90mHz to

107Hz, by writing to the T0/4_Bandwidth registers

(0x1d/0x3a).

3. Holdover

Upon entering holdover mode, the CLK(0-7) clock

outputs are determined from the holdover history

established for the last selected reference, or from a

user supplied holdover history. Output frequency is

determined by a weighted average of the holdover

history, and accuracy is determined by the OCXO/

TCXO. Holdover mode may be entered manually or

automatically. Automatic entry into holdover mode

occurs when operating in the automatic mode, the

reference is lost, and no other valid reference exists.

The transfer into and out of holdover mode is

designed to be smooth and free of hits.

Figure 4: Device phase lock operational mode transi-

tion in Automatic Refernce Selection/Master Mode

DPLL Operating Mode Details

The T0 and T4 clock generators may operate in the

Freerun, Synchronized, or Holdover modes, includ-

ing some variants thereof:

Freerun Mode

The CLK(0-7) clock outputs are synthesized using

the free running OCXO/TCXO, calibrated with the

freerun frequency offset. The calibration offset may

be programmed by the application by writing to the

Freerun_Cal register, (0x0e/0f). The calibration off-

set may be programmed from -102.4 to +102.3 ppm,

in .1ppm steps, in twoâs complement form.

Figure 4 shows the phase lock loop states and transi-

tions for operation with automatic reference selection

in Master mode.

The Freerun mode may be entered automatically,

when in the Automatic Reference Selection mode (as

shown in figure 4), or manually, by writing to the T(0/

4)_Manual_Active_Ref registers.

Data Sheet #: TM084 Page 12 of 44 Rev: P02 Date: 12/5/06

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