STC4130 Datasheet, PDF (25/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

ALE
CS
WRB
RDB
AD
RDY
Symbol
t_RDYd3
Description
RDY high-z delay after CS high
t_ALE
t_ALEd
t_ADs
t_ADh
t_CSs
t_CSd
t_WRB
STC4130
Synchronous Clock for SETS
Data Sheet
Min
Max
Unit
10
nS
t_CSh
Address
t_Ds
t_Dh
Data
t_RDYd1
t_RDYd2
t_RDY
t_WRBh
t_RDYd3
Figure 16: Multiplex Bus Write Timing
Table 11: Multiplex Bus Write Timing
Symbol
t_ALE
t_ALEd
t_ADs
t_ADh
t_CSs
t_WRB
t_CSh
t_CSd
t_Ds
t_Dh
t_RDYd1
t_RDYd2
t_RDY
t_WRBh
t_RDYd3
Description
ALE high time
ALE falling edge to RDB low
Address setup time
Address hold time
Write CS setup time
Write time
CS hold time
CS delay for multiple write/reads
Data setup time
Data hold time
CS low to RDY active
WRB low to RDY low
RDY low time
WRB hold after RDY high
RDY high-z delay after CS high
Min
Max
Unit
10
nS
0
nS
10
nS
10
nS
0
nS
40
nS
10
nS
50
nS
10
nS
10
nS
13
nS
40
nS
50
nS
0
nS
9
nS
Data Sheet #: TM084 Page 25 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice