STC4130 Datasheet, PDF(15/44 Page) List of Unclassifed Manufacturers

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STC4130 Datasheet, PDF (15/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

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Master/Slave Configuration

Pairs of STC4130 devices may be operated in a

master/slave configuration for added reliability, as

shown in Figure 6.

T0_MS

T4_MS

T0 PLL T0_XSYNC_OUT

T0 PLL

T0_XSYNC_IN

T4 PLL

T4_XSYNC_OUT

T4_XSYNC_IN

T4 PLL

STC4130

T0_MS

T4_MS

Figure 6: Master/Slave Configuration

Devices are configured for master/slave operation by

cross-connecting their respective

T(0/4)_Xsync_Out and/or T(0/4)_Xsync_In pins.

The T(0/4)_MS pins determine the master or slave

mode for each clock generator. 1=Master, 0=Slave.

Thus, master/slave state is always manually con-

trolled by the application. The master synchronizes

to the selected input reference, while the slave syn-

chronizes and phase-aligns according to data

received over the T(0/4)_Xsync_Out / T(0/

4)_Xsync_In data link from the unit in master mode.

STC4130

Synchronous Clock for SETS

Data Sheet

may be phase shifted from 0 to +409.5nS, in 100pS

increments according to the contents of the T(0/

4)_Slave_Phase_Adj (0x05/06, 0x07/08) registers

to compensate for the path length of the T(0/

4)_Xsync_Out to T(0/4)_Xsync_In connections.

This offset may therefore be programmed to exactly

compensate for the actual path length delay associ-

ated with the particular application's cross-couple

traces. Thus, master/slave switches with the

STC4130 devices may be accomplished with near-

zero phase hits.

The first time a clock generator becomes a slave,

such as immediately after power-up, its output clock

phase starts out arbitrary, and will quickly phase-

align to the master unit. The phase skew will be elim-

inated (or converged to the programmed phase off-

set) step by step. The whole pull-in-and-lock process

will complete in about 16 seconds. There is no fre-

quency slew protection in slave mode. In slave

mode, the unit's mission is to lock to and follow the

master.

Master T0

Clock

Generator

STC4130

2KHz

8KHz

38.88MHz

77.76MHz

T1/E1

T3/E3

The T0 and T4 PLLâs may be operated completely

independent of each other â either or both may be

cross-connected as master/slave pairs across two

STC4130 devices, and master/slave states may be

set the same or opposite within a given device.

In slave mode, the operational mode is âSynchro-

nizedâ and the T(0/4)_Xsync_Out data links provide

phase and state information. Bits 0 and 1 of the

T0_T4_MS_Sts register reflect the states of the

T(0/4)_MS pins.

Slave T0

Clock

Generator

STC4130

2KHz

8KHz

38.88MHz

77.76MHz

T1/E1

T3/E3

Programmable skew 0 to 409.5 nS

Figure 7: T0 CLK1-6 Phase Alignment and Master/

Slave skew Control

Master/Slave Operation

Perfect phase alignment of the Clk(x) output clocks

(between the clock generators in two devices) would

require no delay on the cross-couple data link con-

nection. To accommodate path length delays, the

STC4130 provides a programmable phase skew fea-

ture. See figures 7 and 8. The slaveâs Clk(x) outputs

Note the phase alignment of all clock outputs from

the T0 clock generator with the 2KHz output.

Data Sheet #: TM084 Page 15 of 44 Rev: P02 Date: 12/5/06

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