STC4130 Datasheet, PDF (37/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

SYNC: Indicates synchronization has been achieved
LOS: Loss of signal
LOL: Loss of lock
OOP: Out of pull-in range
LHC: Long Term History Complete
LHA: Long Term History Available
STC4130
Synchronous Clock for SETS
Data Sheet
T4_Accu_Flush, 0x55 (W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x55
Not used
HO flush
Writing to this register will perform a flush of the accumulated history. The value of bit zero determines which
histories are flushed. Bit 0 = 0, Flush T4 current history only; bit 0 = 1, flush all T4 histories.
CLK0_Sel, 0x56 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x56
Not used
Enables or disables the 155.52MHz CLK0 output.
Default vale: 0.
0=Disable
1=Enable
CLK1_Sel, 0x57 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x57
Selects or disables the CLK1 output.
Not used
CLK1 Select
0x57, bits 1 ~ 0
CLK1 output
Default value: 1.
0
Disabled
1
19.44MHz
2
38.88MHz
3
77.76MHz
Data Sheet #: TM084 Page 37 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice