STC4130 Datasheet, PDF (38/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

STC4130
Synchronous Clock for SETS
Data Sheet
CLK2_Sel, 0x58 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x58
Selects or disables the CLK2 output.
Not used
CLK2 Select
Default value: 2.
CLK3_Sel, 0x59 (R/W)
0x58, bits 1 ~ 0
0
1
2
3
CLK2 output
Disabled
19.44MHz
38.88MHz
77.76MHz
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x59
Not used
CLK3 Select
Selects or disables the CLK3 output, and sets the pulse width. In variable pulse width, the width may be
selected from 1 to 62 times the period of the 155.52MHz output (~6.43nS to 399nS).
Default value: 63.
CLK4_Sel, 0x5a (R/W)
0x59, bits 5 ~ 0
0
1 ~ 62
63
CLK3 8KHz output
Disabled
Pulse width 1 to 62 cycles of 155.52MHz
50% duty cycle
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5a
Not used
CLK4 Select
Selects or disables the CLK4 output, and sets the pulse width. In variable pulse width, the width may be
selected from 1 to 62 times the period of the 155.52MHz output (~6.43nS to 399nS).
Default value: 63.
0x5a, bits 5 ~ 0
0
1 ~ 62
63
CLK4 2KHz output
Disabled
Pulse width 1 to 62 cycles of 155.52MHz
50% duty cycle
CLK5_Sel, 0x5b (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5b
Selects or disables the CLK5 output.
Not used
CLK2 Select
0x5b, bits 1 ~ 0
0
CLK5 output
Disabled
Data Sheet #: TM084 Page 38 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice