STC4130 Datasheet, PDF (26/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

Register Descriptions and Operation
General Register Operation
STC4130
Synchronous Clock for SETS
Data Sheet
The STC4130 device has 1, 2, and 4 byte registers. One byte registers are read and written directly. Two and
four byte registers must be read and written in a specific manner and order, as follows:
Multibyte register reads
A multibyte register read must commence with a read of the least significant byte first. This triggers a transfer
of the remaining byte(s) to a holding resgister, ensuring that the remaining data will not change with the con-
tinuing operation of the device. The remaining byte(s) may then be read in any order, and with no timing restric-
tions.
Multibyte register writes
A multibyte register write must commence with a write to the least significant byte first. Subsequent writes to
the remaining byte(s)must be performed in ascending byte order, but with no timing restrictions. Multibyte reg-
ister writes are temporarily stored in a holding register, and are transferred to the target register when the most
significant byte is written.
Clearing bits in the Interrupt Status Register
Interrupt event register (Intr_Event, 0x5e~0x5f) bits are cleared by writing a “1” to the bit position to be
cleared. Interrupt bit positions to be left as is are written with a “0”.
Default Register Settings
Chip_ID, 0x00 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x00
0x30
0x01
0x41
Chip_Rev, 0x02 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x02
0x01
Chip_Sub_Rev, 0x03 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x03
0x01
Data Sheet #: TM084 Page 26 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice