STC4130 Datasheet, PDF(11/44 Page) List of Unclassifed Manufacturers

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STC4130 Datasheet, PDF (11/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

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beyond the disqualification range will disqualify the

reference. It may then be re-qualified and the activity

alarm is de-asserted, if it is within the qualification

range for more than the qualification time.

The reference qualification status of each reference

may then be read from register Refs_Qual (0x1a/

1b).

Activity Alarm

Asserted

Activity

Not Good

Activity Alarm

De-Asserted

Activity Alarm

Asserted

Within Offset Qualification

Range for more than

Qualification Time

Activity

Good

Qualified

Out of Disqualification Range

STC4130

Synchronous Clock for SETS

Data Sheet

by writing bit 4 of the T0_Control_Mode (0x1c) or

T4_Control_Mode (0x39) register (for T0 or T4,

respectively) to 1.

The reference is picked according to its indicated pri-

ority in the reference priority table, Registers

T0_Priority_Table

(0x31~0x36)

T4_Priority_Table (0x4e ~ 0x0x53). Each reference

has one entry in the table, which may be set to a

value from 0 to 15. â0â masks-out the reference, while

1 to 15 set the priority, where â1â has the highest, and

â15â has the lowest priority. The highest priority pre-

qualified reference is chosen as the active reference.

The automatically selected reference for each DPLL

may be read from registers T0_Auto_Active_Ref

(0x1e) and T4_Auto_Active_Ref (0x3b).

The pre-qualification scheme is described in the Ref-

erence Inputs Monitoring and Qualification sec-

tion. When a selected active reference is

disqualified, the highest priority qualified remaining

reference is chosen. If multiple references share the

same priority, they are ordered according to the dura-

tion of their qualification. The longer the duration, the

higher the priority is set.

Figure 3: Reference Qualification and

Disqualification

DPLL Active Reference Selection

The T0 and T4 clock generators may be individually

operated in either manual or automatic input refer-

ence selection mode. The mode is selected via the

T0(4)_Control_Mode registers.

Manual Reference Selection Mode

In manual reference selection mode, the user may

select the reference. Manual reference selection

mode is selected by setting bit 4 of the

T0_Control_Mode (0x1c) or T4_Control_Mode

(0x39) register (for T0 or T4, respectively) to 0. The

reference is selected by writing to bits 0 - 3 of the

T0_Manual_Active_Ref

(0x1f)

and

T4_Manual_Active_Ref (0x3c) registers.

Automatic Reference Selection Mode

In automatic reference selection mode, the device

will select one pre-qualified reference as the active

reference. Automatic reference selection mode is set

When a reference is disqualified, and subsequently

re-qualified as the highest priority candidate, it may

or may not be re-selected as the active reference.

This is determined by either enabling or disabling

âreversionâ by writing bit 3 of the T0_Control_Mode

(0x1c) or T4_Control_Mode (0x39) register (for T0

or T4, respectively) to â1â for revertive or to â0â for

non-revertive operation.

If reversion is enabled, a qualified/re-qualified refer-

ence will be selected as the new active reference, if it

is the highest priority qualified reference at that time.

If reversion is disabled, the active reference will not

be pre-empted by a higher priority reference until it is

disqualified.

Digital Phase Locked Loop General

Description

The STC4130 includes both a T0 and T4 clock gen-

erator. Each clock generator has a DPLL, including a

phase detector and a digital filter.

Each DPLL may select any of the 12 input reference

clocks in master mode. In slave mode, they will

Data Sheet #: TM084 Page 11 of 44 Rev: P02 Date: 12/5/06

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