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M13S2561616A_1 Datasheet, PDF (8/49 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
ESMT
M13S2561616A
Operation Temperature Condition -40~85°C
AC Timing Parameter & Specifications-continued
Parameter
Symbol
-5
-6
min
max
min
max
ns
Half Clock Period
tHP
tCLmin or
tCHmin
-
tCLmin or
tCHmin
-
ns
DQ-DQS output hold time
tQH
tHP-tQHS
-
tHP-tQHS
-
ns
Data hold skew factor
tQHS
-
0.5
-
0.55
ns
ACTIVE to PRECHARGE
command
tRAS
40
70K
42
70K
ns
Row Cycle Time
tRC
55
-
60
-
ns
AUTO REFRESH Row Cycle
Time
tRFC
70
-
72
-
ns
ACTIVE to READ,WRITE
delay
tRCD
15
-
18
-
ns
PRECHARGE command
period
tRP
15
-
18
-
ns
ACTIVE to READ with
AUTOPRECHARGE
command
tRAP
18
120K
18
120K
ns
ACTIVE bank A to ACTIVE
bank B command
tRRD
10
-
12
-
ns
Write recovery time
tWR
15
-
15
-
ns
Write data in to READ
command delay
tWTR
2
-
1
-
tCK
Col. Address to Col. Address
delay
tCCD
1
-
1
-
tCK
Average periodic refresh
interval
tREFI
-
7.8
-
7.8
us
Write preamble
tWPRE
0.25
-
0.25
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Clock to DQS write preamble
setup time
tWPRES
0
-
0
-
ns
Load Mode Register /
Extended Mode register
tMRD
2
-
1
-
tCK
cycle time
Exit self refresh to READ
command
tXSRD
200
-
200
-
tCK
Exit self refresh to
non-READ command
tXSNR
75
-
75
-
ns
Autoprecharge write
recovery+Precharge time
tDAL
30
-
-
30
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
8/49