M13S2561616A_1 Datasheet, PDF (4/49 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S2561616A
Operation Temperature Condition -40~85°C
Pin Description
60 Ball BGA
1
2
3
A ^{VSSQ DQ15 VSS}
7
8
9
VDD DQ0 VDDQ
B ^{DQ14 VDDQ DQ13}
DQ2 VSSQ DQ1
C DQ12 VSSQ DQ11
DQ4 VDDQ DQ3
D DQ10 VDDQ DQ9
DQ6 VSSQ DQ5
E DQ8 VSSQ UDQS
LDQS VDDQ DQ7
F VREF VSS UDM
LDM VDD NC
G
CLK CLK
WE CAS
H
A12 CKE
J
A11 A9
K
A8
A7
L
A6
A5
M
A4
VSS
RAS ^CS
BA1 BA0
A0 A10/AP
A2
A1
VDD
A3
Pin Name
A0~A12,
BA0,BA1
DQ0~DQ15
RAS
CAS
WE
V_SS
V_DD
LDQS, UDQS
Function
Address inputs
- Row address A0~A12
- Column address A0~A8
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
Pin Name
Function
LDM, UDM
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
CLK, CLK
CKE
CS
V_DDQ
V_SSQ
V_REF
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL-2
NC
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
4/49