M13S2561616A_1 Datasheet, PDF (45/49 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Power up & Initialization Sequence
0
1
2
3
4
5
6
CLK
CLK
7
8
M13S2561616A
Operation Temperature Condition -40~85°C
9
10
11 12
13 14 15 16 17
18 19
CKE
High level is required
CS
RAS
CAS
WE
BA0
BA1,A9,
A11,A12
A10/AP
A8
A7
A1~A6
ADDRESS KEY
A0
High-Z
DQ
DQS
tRP
High-Z
Precharge
EMRS
All Bank DLL Enable
(Power & Clock must be
stable for 200us
before Precharge
All Bank)
MRS
DLL Reset
Minimum 200 Cycle
tRP
tRFC
tRFC
Minimum of 2 Refresh Cycles are required
Precharge
All Bank
1st Auto Refresh
2nd Auto Refresh
Any
Command
Mode Resister Set
: Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
45/49